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IP / SOC Products Articles

• Guide to Choosing the Best DCDC Converter for Your Application (Mar. 28, 2016)
  This white paper introduces a procedure for choosing the proper DCDC switching converter for a given application. It explains basic, performance, and optional metrics in detail. It also demonstrates other practical aspects that are sometimes overlooked by system designers. Multiple application examples are provided.
  
  
• NVMe IP for Enterprise SSD (Mar. 24, 2016)
  Most of SSD manufacturers jumped into this new storage market with flash-based technology. A second wave of products will come in the near future, using a new generation of non-volatile memories, delivering impressive speed performances compared to NandFlash memories. The SSD manufacturers will have to deal with low latency SSD controller design in order to benefit from the new NVM features, while keeping high reliability and low power consumption. This white paper proposes a solution based on a full hardware NVMe implementation, describing its architecture, implementation and characterization.
  
  
• LPDDR4: Now and for Next Generation (Mar. 14, 2016)
  Technology has leapt several folds. Looking at the communication industry, it has steadily advanced from the heavy gadgets that had only calling and texting facilities, a poor battery life only made matters worse. This industry however has led to many research works and innovations, the phones that were once meant only for calling are now capable of doing so much, calling is now a secondary feature. Mobile device user is using so many applications in parallel which in turns demands more powerful processing unit and faster, bigger memory.
  
  
• A versatile Control Network of power domains in a low power SoC (Mar. 10, 2016)
  Developing and verifying a control network in a low-power SoC is a challenging task, especially managing the different states of regulators and modes of power domains. This article first describes state-of-the-art approaches to addressing this issue, and then delves into the solution promoted by Dolphin Integration to go further, thanks to the easy and secure Maestro� solution to manage SoC power mode transitions.
  
  
• D32PRO, scalable & royalty free 32-bit CPU (Mar. 03, 2016)
  D32PRO is one of the newest 32-bit CPUs available on the market. It’s been designed by Digital Core Design, IP Core provider and SoC design house from Poland, responsible e.g. for the world’s fastest or world’s smallest 8051 CPU. DCD launched more than 70 different architectures since 1999, which have been implemented in more than 300 000 000 electronic devices, that’s why one can be sure that quite considerable experience stands behind the D32PRO.
  
  
• It's Alive! The Miraculous Resurrection of Artificial Intelligence (Feb. 29, 2016)
  New results on fronts as diverse as playing human games, identifying photos of objects, showing awareness of situations, and control of autonomous vehicles are all showing promise. Will this time be different?
  
  
• Designing AC/DC Adaptors for USB Type-C Power (Feb. 29, 2016)
  After much discussion, products with new USB Type-C (Type-C) ports are finally here! In 2015, Apple's new MacBook and Google's Nexus 6P were released with the new USB-C port.
  
  
• Designing an Efficient DSP Solution: Choosing the Right Processor and Software Development Toolchain (Feb. 22, 2016)
  This white paper describes how to generate tight, efficient, and maintainable DSP code for a platform consisting of an IP core based on a specialized instruction-set architecture (ISA) coupled with a DSP-aware toolchain.
  
  
• Securing the Most Important Goal of USB Type-C Technology: A Better User Experience (Feb. 17, 2016)
  Now that the USB Type-C™ Cable and Connector Specification is starting to reach the masses, the world of advanced technology and hundred-pages-thick specifications finally meets the world of casual users. The initial impression is that while device owners appreciate the new features and ease of use, they are more puzzled than before with incompatibility of devices, dangerously bad cables, and the need for adapters for their old devices. What do we, as an industry, need to do to overcome these fears and secure a path to USB Type-C success?
  
  
• Leverage always-on voice trigger IP to reach ultra-low power consumption in voice-controlled devices (Feb. 15, 2016)
  Due to the lack of thorough specifications to assess the performance of voice detection solutions, it is a real conundrum for users to evaluate the best solution among a jungle of true and false detection claims and without any benchmark. ?The aim of this article is to help IP procurement managers, SoC architects and system makers using voice detection IP in their systems to assess and compare the detection performances.
  
  
• Delivering High Quality Analog Video Signals With Optimized Video DACs (Feb. 15, 2016)
  This paper outlines the most common analog video signal standard-specifications that multimedia SoCs must support. It describes the key characteristics and features of a DAC solution optimized for video applications. The paper addresses system-level techniques that together with an optimized video DAC will enable SoC designers to deliver power-efficient and feature-rich multimedia devices.
  
  
• Custom ASICs for Internet of Industrial Things (IoIT) (Feb. 11, 2016)
  This white paper commences with an overview of the IoIT (Internet of Industrial Things) opportunity, the market drivers, and how the semiconductor industry is responding to this need. We then include an example of a customisable SoC intended for use in various industrial applications where low power consumption, remote deployment, reduced production costs and short time-to-market are vital.
  
  
• Optimizing LPDDR4 Performance and Power with Multi-Channel Architectures (Feb. 08, 2016)
  
  
  
• Opportunities and Challenges for Near-Threshold Technology in End-Point SoCs for the Internet of Things (Feb. 04, 2016)
  Qian Yu, Technical Marketing Manager at ARM, discusses the potential of near-threshold technology to enable the lowest possible power consumption to extend battery life for end-point devices deployed in the Internet of Things. He also reviews some of the challenges including integrating memory and attaining necessary support from semiconductor foundries and EDA vendors to make ultra-low-power, near-threshold design a reality.
  
  
• Interconnect: Switzerland of IP (Feb. 01, 2016)
  The IP and EDA industries need an independent, neutral provider of interconnect IP technology to provide a level playing field for other IP companies
  
  
• Addressing Three Critical Challenges of USB Type-C Implementation (Feb. 01, 2016)
  As designers create new products and system-on-chips (SoCs) with USB Type-C support, they need to be aware of datapath and hardware/software partitioning challenges.
  
  
• Reusable MAC Design for Various Wireless Connectivity Protocols (Jan. 25, 2016)
  This paper presents how the 8-bit customized micro-processor could implement the MAC operation that sufficiently co-processes with main CPU as well as meets the timing requirement for controlling various PHY and RF. Because IEEE 802.11ac VHT MAC is the most challengeable protocol to be designed by SW among the introduced connectivity technologies, we evaluated our MAC design with VHT MAC protocol and generated several constraints, which are not critical points to our programmable and common platform concepts.
  
  
• How a 16Gbps Multi-link, Multi-protocol SerDes PHY Can Transform Datacenter Connectivity (Jan. 21, 2016)
  Increasingly, more of the focus on mobile has centered around cloud datacenters and the networking to get the data back and forth between these datacenters and the mobile device. Functions like voice recognition and mapping depend on the ability to split the functionality between the smartphone, for local processing like encryption and compression, and the back end, where a large number of servers can do the heavier lifting before returning the results.
  
  
• True Random Number Generators for Truly Secure Systems (Jan. 18, 2016)
  Random numbers form the basis, or root, of most security systems. Yet the methods for generating random numbers vary widely in practice as well as efficacy.
  
  
• NoC Interconnect Fabric IP Improves SoC Power, Performance and Area (Jan. 18, 2016)
  Imagine you have defined the structure of a system-on-chip and now you have to assemble all the IP blocks and make them communicate on the die. You have spent months rigorously selecting SoC IP that reflects the desired chip functionality. However, without the on-chip interconnect fabric it is just a collection of isolated blocks.
  
  
• Modeling and Verification of Mixed Signal IP using SystemVerilog in Virtuoso and NCsim (Jan. 11, 2016)
  In this paper we present a methodology to model and verify a mixed-signal IP using SystemVerilog in Virtuoso and NCsim. We take our 12.5Gbps transmitter (TX) design as an example to explain the method we propose. This TX is designed to operate at programmable data rates from 1.25Gbps – 12.5Gbps and to support requirements of multiple serial protocols like USB, PCIe, and SATA. Interaction between AFE and Digital is key towards proper implementation of features like Feed Forward Equalization (FFE), programmable output swing and power management states.
  
  
• DFT strategy for IPs (Jan. 11, 2016)
  IPs (Building blocks of ASIC/SoC e.g. CPU, GPU) build and sign off in a wider sense. It doesn’t always mean Chip Timing, Design Rule Constraints & Power Closure of a block, but also refers to the creation of a layout/partition around the delivered build/sign off IPs/blocks. This would further refer to flows that are planned, library composition, various floorplan styles and shapes.
  
  
• Enable IoT ASIC Design Using Platforms (Jan. 08, 2016)
  The Internet of Things (IoT) hype is now getting real. This, in turn, is creating the opportunity to move from off-the-shelf chip designs to custom silicon. The key to creating cost-effective, custom silicon for the IoT will be the platform approach.
  
  
• USB Type-C: Is it all just Hype-C for embedded designers? (Dec. 14, 2015)
  Will the do-it-all connector standard maintain its blazing fast adoption?
  
  
• Tech Overhaul: An Ode to Faster Memories (Dec. 14, 2015)
  With the advent of technology the globe is shrinking. Technology has leapt many bounds and brought almost everything thinkable at one’s fingertips. Amongst various spheres of Technology the communication industry takes the cake, for every advent here is awaited with bated breath.
  
  
• Soft-Decoding in LDPC based SSD Controllers (Dec. 08, 2015)
  What happens when that initial decode fails? How soft data can be used to recover data on the SSD.
  
  
• How to Ensure a Bug Free BootROM? (Nov. 30, 2015)
  In this article, we outline the robust testing of BootROM by churning out best capabilities of three powerful platforms – SoC simulation, Hardware emulation, and EVB Validation.
  
  
• Breakthrough in Microprocessor Architecture and Energy Performance (Nov. 26, 2015)
  Radically new processor architecture, reducing overhead high frequency switching, is needed in order to fully utilize the potential of future CMOS technology. Optimizing for energy efficiency, performance, cost, code density, adaptability and scalability are big challenges for the microprocessor architect. Imsys has developed a dual core processor with features not found in other architectures and it is runtime reconfigurable.
  
  
• Efficient logic optimization utilizing complementary behavior of CMOS gates (Nov. 23, 2015)
  Any typical digital design style with CMOS uses complementary pairs of p-type and n-type MOSFETs for logic functions implementation. Naturally, CMOS always ought to provide INVERTED outputs like Inverter, NAND, NOR etc. Sometimes a non-inverting function is required, in which case it's just as easy to implement it with a final inverter or with a non-inverting function like AND, OR.
  
  
• Safety in SoCs: Accelerating the Road to ISO 26262 Certification for the ARC EM Processor (Nov. 23, 2015)
  This white paper outlines the key requirements for ISO 26262 certification and demonstrates how to accelerate the development of safety-critical IP and SoCs through the use of out-of-the-box safety-ready IP with advanced verification qualification tools and methodologies.