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IP / SOC Products Articles

• Design trade-offs of using SAR and Sigma Delta Converters for Multiplexed Data Acquisition Systems (Nov. 18, 2015)
  Multiplexed data acquisition systems (DAS) utilized in industrial process control, portable medical devices and optical transceivers need increased channel density, where the user wants to measure the signals from multiple sensors and monitor and scan many input channels in to a single or several ADCs.
  
  
• Low-complexity compression solves video challenges (Nov. 16, 2015)
  Advances in image sensors and camera technology promise to make your video applications more sensitive, with better-quality images at higher frame rates. However, this also means that more bits have to be streamed, analyzed, kept in memory, or stored for archiving. In short, you’ll need more bandwidth, expensive cabling, and new storage solutions. A smart solution to avoid these challenges is to use a lightweight, mezzanine compression, a compression that allows transporting and storing video at high quality but also at a reasonable cost, possibly even on your existing equipment.
  
  
• Greater Debug of a SoC having heterogeneous ARM Core's (Nov. 09, 2015)
  This article describes a high visibility and non-invasive debug architecture having Quad Core ARM Cortex A9 and Dual Core ARM cortex R4 cores. This debug architecture implements ARM Coresight components to enable seamless debug capability and external trace support. ARM Coresight technology and the components are re-used for debug purposes in various SOC’s having ARM cores.
  
  
• USB 3.1 implementation of USB Type-C (Nov. 05, 2015)
  This article discusses how to implement a USB Type-C port so that it will minimally impact an existing system.
  
  
• Complex SoCs: Early Use of Physical Design Info Shortens Timing Closure (Nov. 02, 2015)
  Chip designs are becoming so complex that they are extremely difficult to implement in the physical design stage. Predicting trouble spots beforehand is paramount.
  
  
• Firmware Compression for Lower Energy and Faster Boot in IoT Devices (Oct. 26, 2015)
  The phrase “IoT” for Internet of Things has exploded to cover a wide range of different applications and diverse devices with very different requirements. Most observers, however, would agree that low energy consumption is a key element for IoT, as many of these devices must run on batteries or harvest energy from the environment.
  
  
• Designing High Performance Interposers with 3-port and 6-port S-parameters (Oct. 19, 2015)
  This paper will interpret multiport S-parameters for several memory interposer design cases. This will help the audience understand some of the performance characteristics that can be inferred from the S-parameters, as well as some of the interactions between the interposer and the device under test and probing system
  
  
• Architect a Next-Gen 802.11ac Wave 3 Software-Defined Modem (Oct. 12, 2015)
  This paper presents an evolution of the RivieraWaves Stream architecture for next-generation 802.11 ac Wave 3, which can support complex configurations up to 8x8 MU-MIMO with 160MHz bandwidth.
  
  
• Supply Noise Induced Jitter - Don't Let it Kill your Chip (Sep. 28, 2015)
  This presentation is about a problem we at Silicon Creations have seen quite often when our, or others’ PLLs are used in complex SoCs. Although the design team usually implements the PLL correctly in the chip with the right supplies connected the right ways, we have often seen that designers overlook the significant impact that their floorplan and power supply plan have on the clock as it travels from the PLL to the circuits the PLL is clocking.
  
  
• USB 3.1 Gen 2 Brings Higher Data Rates with Architecture Improvements (Sep. 28, 2015)
  In this article, let's take a closer look at the application architecture impact of the USB 3.1 specification - namely, the changes that need to be introduced to take advantage of the improved bandwidth that you can get from integrating USB 3.1 Gen 2 support in your designs.
  
  
• Methods to Fine-Tune Power Consumption of PCIe devices (Sep. 21, 2015)
  This paper will examine the various design elements, design techniques and PCI Express optional features that can be leveraged to reduce a device’s power consumption without compromising performance.
  
  
• Implementing Ultra Low Latency Data Center Services with Programmable Logic (Sep. 21, 2015)
  Data centers require many low-level network services to implement high-level applications. Key-Value Store (KVS) is a critical service that associates values with keys and allows machines to share these associations over a network. Most existing KVS systems run in software and scale out by running parallel processes on multiple microprocessor cores to increase throughput.
  
  
• LBIST - A technique for infield safety (Sep. 21, 2015)
  In this article, we will be discussing how LBIST testing differs from conventional testing, some important applications of LBIST and design overhead of using LBIST in the design.
  
  
• All you need to know about MIPI D-PHY RX (Sep. 16, 2015)
  MIPI D’Phy, a physical serial communicating layer connecting the application processor to the display device or the camera, offers advantages as the physical layer.
  
  
• UFS Goes Mainstream (Sep. 14, 2015)
  UniversalFlash Storage (UFS) was created for mobile applications and computer systems requiring high performance and low power consumption. These systems typically use embedded Flash based on the JEDEC standard eMMC. UFS was defined by JEDEC as the evolutionary replacement for eMMC offering significantly higher memory bandwidth. The standard builds on existing standards such as the SCSI command set, the MIPI Alliance M-PHY and UniPro as well as eMMC form factors to simplify adoption and development.
  
  
• Anatomy of the HDMI IP Certification Flow (Sep. 07, 2015)
  This white paper outlines the HDMI IP certification flow from internal quality, functionality and interoperability testing to certification of the latest HDMI Compliance Test Specification (CTS) at an Authorized Test Center (ATC).
  
  
• An Automated Flow for Reset Connectivity Checks in Complex SoCs having Multiple Power Domains (Sep. 07, 2015)
  Today’s SoC designers are designing chips which have an optimum balance between performance and power numbers. So, the whole SoC design is divided into different power domains having a set of modules present in each of them. The power domains can be kept powered-on in some modes of operations and can be power gated in some other modes of operations.
  
  
• Meeting IP Requirements of New Auto SoCs (Sep. 03, 2015)
  To implement the advanced protocols required to meet high performance operation, the ADAS SoCs use design and process technologies that are more stringent than most high-end consumer applications.
  
  
• Method for Booting ARM Based Multi-Core SoCs (Aug. 31, 2015)
  In the boot process various modules/peripherals (like clock controller or security handing module and other master/slaves) initialized as per the SoC architecture and customer applications. In Multi core SoCs, first primary core (also called booting core) start up in boot process and then secondary cores are enabled by software.
  
  
• USB Power Delivery 2.0 Enables Power Distribution Flexibility (Aug. 31, 2015)
  The latest USB 3.1 specification increases the current capability to 900mA if legacy Type-A connectors are used. If the new Type-C connector - which has four power/ground pairs - is employed with USB 3.x, the current rating can be as high as 3A, but still at only 5V.
  
  
• Save power in IoT SoCs by leveraging ADC characteristics (Aug. 27, 2015)
  Power-sensitive applications such as Internet-of-Things (IoT) require a comprehensive power savings strategy within the system-on-chip (SoC). Techniques relying solely on the use of traditional power down modes and low supply voltage may not be enough to achieve the required power targets. The analog block is often assumed to be too sensitive and not compatible with aggressive power management techniques.
  
  
• Clock Gating Checks on Multiplexers (Aug. 24, 2015)
  With the increasing complexity of design in today’s fast changing world, the thrust on power saving has increased manifold. Consequently, gating the most toggling signal on the SoC i.e. the clock has become the norm now rather than an exception. From timing perspective, clock gating brings some challenges and some special considerations.
  
  
• PLL Subsystem architectures for SoC design (Aug. 24, 2015)
  Because of the cornerstone importance of PLLs to an SoC design, this article considers the various challenges in the design of PLL subsystems, and discuss architectural solutions.
  
  
• 7 Steps to a Successful Analog ASIC (Aug. 20, 2015)
  I’m willing to bet that there are tens of thousands of analog applications out there that would benefit financially from ASIC integration. So what’s the holdup? Based on my 40+ years in the Analog IC business, I can boil it down to one word. Misinformation. This is a combination of a lack of information, incorrect information, and of course, FUD (Fear, Uncertainty and Doubt).
  
  
• High Speed ADC Data Transfer (Aug. 17, 2015)
  When continuously running a high speed ADC, it can be a challenge to deal with the firehose of raw data available at the output. To use City Semiconductor’s 2.5 GS/s 12-bit ADC, for example, 30 gigabits per second of data have to be accepted.
  
  
• Motion Picture: a Reality on Emulation Platform (Aug. 17, 2015)
  In present day’s situation, whenever we are in the phase of designing a cluster SoC, we have no reliable way of verifying our design in real case scenarios, or showcase the possibilities of our design through any demos. This, sometimes, paves way for critical design bugs which requires re-spins/cuts.
  
  
• Floating-point FFT with Minimal Hardware (Aug. 10, 2015)
  Here we discuss Centar’s floating-point FFT technology which provides IEEE754 single-precision outputs, yet is much more hardware efficient. For example in the FPGA domain, which is the focus of this note, comparisons show that other designs use up to 100% more logic elements. Such reduced hardware can move the tradeoffs between fixed and floating-point attractively in the direction of the floating-point option. Centar’s design also has better numerical properties.
  
  
• Effective Timing Strategies for Increasing PCIe Data Rates (Jul. 30, 2015)
  The PCIe standard has become a popular choice for high-speed serial communication but as successive generations of the standard offer increased data rates, reference clock performance is becoming progressively more critical and the specifications more aggressive to ensure good timing margins.
  
  
• Chips in Space -- MacSpace, A Record Throughput Multi-Core Processor for Satellites (Jul. 30, 2015)
  MacSpace is a collaborative R&D project aiming to research and develop a many-core DSP chip and computer for use in space.
  
  
• The Hard Facts about Soft Interconnect IP (Jul. 27, 2015)
  Building world-class Network-on-Chip interconnect IP and configuration tools is difficult, time consuming and capital intensive