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IP / SOC Products Articles

• High Speed ADC Data Transfer (Aug. 17, 2015)
  When continuously running a high speed ADC, it can be a challenge to deal with the firehose of raw data available at the output. To use City Semiconductor’s 2.5 GS/s 12-bit ADC, for example, 30 gigabits per second of data have to be accepted.
  
  
• Motion Picture: a Reality on Emulation Platform (Aug. 17, 2015)
  In present day’s situation, whenever we are in the phase of designing a cluster SoC, we have no reliable way of verifying our design in real case scenarios, or showcase the possibilities of our design through any demos. This, sometimes, paves way for critical design bugs which requires re-spins/cuts.
  
  
• Floating-point FFT with Minimal Hardware (Aug. 10, 2015)
  Here we discuss Centar’s floating-point FFT technology which provides IEEE754 single-precision outputs, yet is much more hardware efficient. For example in the FPGA domain, which is the focus of this note, comparisons show that other designs use up to 100% more logic elements. Such reduced hardware can move the tradeoffs between fixed and floating-point attractively in the direction of the floating-point option. Centar’s design also has better numerical properties.
  
  
• Effective Timing Strategies for Increasing PCIe Data Rates (Jul. 30, 2015)
  The PCIe standard has become a popular choice for high-speed serial communication but as successive generations of the standard offer increased data rates, reference clock performance is becoming progressively more critical and the specifications more aggressive to ensure good timing margins.
  
  
• Chips in Space -- MacSpace, A Record Throughput Multi-Core Processor for Satellites (Jul. 30, 2015)
  MacSpace is a collaborative R&D project aiming to research and develop a many-core DSP chip and computer for use in space.
  
  
• The Hard Facts about Soft Interconnect IP (Jul. 27, 2015)
  Building world-class Network-on-Chip interconnect IP and configuration tools is difficult, time consuming and capital intensive
  
  
• Cheaper, Denser NAND Requires Better Error Correction (Jul. 22, 2015)
  Here's why PMC-Sierra switched from Bose-Chaudhuri-Hocquenghem codes to low-density parity check (LDPC) codes for error correction in its solid-state drive controllers.
  
  
• Device Malfunction due to Faulty Digital circuit along with suggested Remedies (Jul. 20, 2015)
  Using of basic building blocks in different ways to make complex circuit is a common axiom in Digital Logic design. The complexity of these building blocks can vary from simple structure like synchronizers, multiplexers, adders, FIFO, Glitch-free multiplexer to complex circuits like custom CDC Module, Encoders, decoders etc.. If we talk about these circuits, there exist countless designs, each of them depending on the requirement- any implementation working in one scenario may fail or put limitations in other scenario. This paper intends to discuss some of the commonly used circuits which are faulty in certain scenario and various remedies to make those circuits more robust to increase their acceptability.
  
  
• The Evolution of Object Recognition in Embedded Computer Vision (Jul. 13, 2015)
  Object detection and recognition are an integral part of computer vision systems. In computer vision, the work begins with a breakdown of the scene into components that a computer can see and analyse.
  
  
• Debugging LBIST safe-stating issues (Jul. 13, 2015)
  Logic built-in self test (LBIST) allows hardware to test its own operation. There is no need for any external hardware or test equipment. LBIST is a “must have” feature for safety compliant SoCs. But care must be exercised when using LBIST in a complex SoC.
  
  
• Configurable Asynchronous Set/Reset Flip-Flop for Post-Silicon ECOs (Jul. 06, 2015)
  This paper proposes a configurable asynchronous set/reset flip-flop design that tends to resolve the timing and implementation issues concerned with such post-silicon metal ECOs and compares the existing solutions against the proposed one to evaluate its benefits.
  
  
• Reset connectivity checks in complex low power architectures (Jul. 06, 2015)
  In this article we are explaining the checks that should be done to catch such power domain related reset connectivity issues.
  
  
• Ethernet as IP: The Time Has Come (Jun. 29, 2015)
  In this paper, we will look at the economics of integrating the Ethernet Physical Layer, and what options exist for product managers and engineers seeking to shrink their power and area footprints, while achieving cost reduction
  
  
• Ten reasons interconnect matters (Jun. 25, 2015)
  Interconnect is the Rodney Dangerfield of IP blocks. It gets no respect. It connects hundreds of disparate IP blocks, each with hundreds of interface signals, and dozens of transaction protocol attributes. It does it in a way that each IP need not know the protocol details of any other. It also provides for the data access requirements of each IP, and does it physically distributed across the chip floorplan. Interconnect fabric technology is sophisticated, and very important for modern chip designs. Following are ten reasons why interconnect matters.
  
  
• Reducing chip IR drop in backward-compatible power bar-limited LQFP SoCs (Jun. 24, 2015)
  SoC design comes with its own set of complications and challenges. One of the biggest challenges that arises is backwards-compatible power bar-limited design in an LQFP package.
  
  
• Efficient methodology for design and verification of Memory ECC error management logic in safety critical SoCs (Jun. 22, 2015)
  This paper presents the efficient methodology to implement and verify ECC error management in systems with large number of memories, with minimum hardware overhead and without compromising the safety requirements.
  
  
• High Speed Data Recorder (Jun. 15, 2015)
  A new IP Core from ASICS World Services, provides a complete high speed data recorder, in one easy to use block.
  
  
• An efficient way of loading data packets and checking data integrity of memories in SoC verification environment (Jun. 08, 2015)
  This paper discusses about the requirement for backdoor loading and comparison of processed data (in digital verification environment) and explains a method to implement such a scheme, which saves a lot of simulation time, while maintaining the data integrity.
  
  
• A Case Study - RF ASIC Validation of a satellite transceiver (May. 27, 2015)
  ASIC validation in the RF world comes with its own set of hurdles and challenges, with high quality lab equipment, experience and know-how essential. A recently completed RF sub-system validation at S3 Group is presented in the form of a case study of the execution.
  
  
• Safety intended Re-configurable Automotive microcontroller with reduced boot-up time (May. 21, 2015)
  This paper addresses these issues associated with partial power failures. It proposes a technique using which the user can get a basic warning that there is a failure and can also diagnose the problem, enhancing safety. Also the user can run small applications if needed.
  
  
• Latest Version of Interface Protocol Speeds Mobile Device Development, Lowers e-BoM (May. 18, 2015)
  Originally designed for mobile devices with limited power and high functionality, LLI technology is now applicable to a broader range of devices that require improved chip-to-chip functionality between master and companion chips. LLI v2.1 allows two devices on separate chips to communicate as if a device attached to the remote chip actually resides on the local chip. This allows memory sharing between chips, which reduce the electronic bill of materials (e-BoM).
  
  
• Verification Challenges of High Speed Interfaces (May. 18, 2015)
  This paper talks about the Pre-Si verification challenges of JESDPHY, USB PHY; the solutions we came up with; and the bugs that were caught in the early in the design cycle with our approach.
  
  
• Design Implications of USB Type-C (May. 13, 2015)
  USB Type-C is a very big deal for the USB community and IP developers. What are the gotchas? Is there no pain with this gain?
  
  
• How Random is Random Enough For Cryptography? (May. 12, 2015)
  How can one create a random stream of bits suitable for use in encryption and embed this solution in an FPGA?
  
  
• A High Efficiency Referencing Frame Buffer Compression IP for H.265 Video Codec (May. 11, 2015)
  A 3.0X times image compression method and fast storage device accessing H.265 referencing image frame is achieved by applying fixed bit rate to reduce each “Block of pixels” data of each image frame. Several thresholds are quality predetermined depending on the availability of the bandwidth of the storage device and the image resolution to decide the compression ratio of each image frame
  
  
• Risks and Precautions to take care while using On-Chip temperature sensors in Safety critical automotive applications (May. 11, 2015)
  Automotive electronics have to sustain harsh conditions like temperature and noisy Environment. The aim these days is to place the electronics as near to engine and transmission control unit as possible so that their noise effect is minimal. This in turn creates another challenge that electronics have to survive very high temperature as engine and transmission control unit can raise the temperature significantly.
  
  
• A look into Bluetooth v4.2 for Low Energy Products (May. 05, 2015)
  The Bluetooth v4.2 Specification was officially adopted in December of 2014 by the Bluetooth Special Interest Group (Bluetooth SIG) and it brings a host of updates to Bluetooth Low Energy (BLE) or Low Energy (LE) for short. Although no Bluetooth chipset vendor is officially supporting it yet, support will make its way into devices in the next few quarters. There are quite a few updates in the v4.2 specification, and we’re going to go over them and how they can affect your product and design decisions.
  
  
• Efficient methodology for verification of Dynamic Frequency Scaling of clocks in SoC (May. 04, 2015)
  In this paper, an approach has been given to verify the integration and functionality of Dynamic Frequency Scaling in the SoC using multiple checks like assertions, frequency monitors and randomized test cases which we can use in the testbench environment. With this approach, multiple design bugs have been uncovered in the SoCs.
  
  
• Rethinking the Internet of Things (Apr. 30, 2015)
  As the Internet of Things (IoT) cements itself into place as the mandatory next big thing for 2015, more systems architects are taking a hard look at its underlying concepts. As they look, these experts are asking some hard questions about simplistic views of the IoT structure: the clouds of sensors and actuators attached to simple, low-power wireless hubs, linked through the Internet to massive cloud data centers.
  
  
• Method to minimize switching activity in digital data transfer protocols (Apr. 27, 2015)
  Parallel Data transfer using digital hardware involves a significant amount of switching power consumption, which increases as “data activity” increases. The motivation was to reduce switching noise in areas where parallel data packet transfer is involved, e.g., reading sectors of Flash memory, inter-processor communication, etc