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IP / SOC Products Articles

• Improve FPGA communications interface clock jitters with external PLLs (Sep. 29, 2014)
  In this Product-How-To article, IDT’s Fred Hirning describes the problems faced in dealing with clock jitter in FPGA-based high-speed communications interfaces such as SerDes and how external phase locked loops (PLLs) such as the company’s VersaClock5 and FemtoClock NG clock generator can be used to resolve them.
  
  
• Understanding layers in the JESD204B specification: A high speed ADC perspective, Part 1 (Sep. 25, 2014)
  In this two-part article, the author will help designers understand how high speed ADCs can properly use and understand how to use to your design advantage the JESD204B standard for the ADC to FPGA interface. Part 1 will discuss an Introduction and Data Flow through the layers of the JESD204B interface, as well as the Application and Transport layers discussed in depth.
  
  
• Product how-to: Reliable SoC bus architecture improves performance (Sep. 24, 2014)
  This paper describes a modeling project to architect the bus topology and evaluate the read/write traffic patterns for a new multimedia System-On-Chip. Using the selected modeling and simulation exercise, we were able to validate the entire architecture in three months. In the process, we learned about architecture behavior and were able to test a large number of operating scenarios to achieve optimum performance in minimal time.
  
  
• RISC-VLIW IP Core for the Airborn Navigation Functional Oriented Processor (Sep. 22, 2014)
  Development of miniature high performance data processing systems needs combined optimization of algorithms and processor architecture. Today's microelectronics allows designing almost all the computer architectures as SoC. The paper is devoted to the practical realization of SINS algorithms by means of SoC.
  
  
• Low-loss compression of CPRI baseband data (Sep. 19, 2014)
  This paper describes a method of using Mu-Law compression for Gaussian-like waveforms – for example, baseband IQ data, as used in CPRI interfaces.
  
  
• Reducing Power Consumption while increasing SoC Performance (Sep. 15, 2014)
  Designers of today's high-performance multi-client SoCs struggle to achieve the best possible performance/watt for their designs. Every generation of product must improve the customer's user experience by delivering more performance. While at the same time battery life must increase with each subsequent product generation.
  
  
• What is 802.11ac, anyway? (Sep. 11, 2014)
  IEEE 802.11ac has a lot to add to the wireless family. It brings a significant improvement over 802.11n. What are the differences between 802.11n and 802.11ac?
  
  
• An innovative methodology to reduce routing capacitance of ADC channels (Sep. 08, 2014)
  As the technology nodes are shrinking, achieving performance metrics for analog circuits are becoming more challenging. Moreover RLC parasitic and noise effects have hampered the performance of circuits on SoC, especially for the sensitive analog circuits like ADCs, Oscillators etc. With more and more complex designs with frequencies in Ghz range, noise sources have increased considerably which affects the intended behavior of the signal.
  
  
• Semiconductor innovations in computer vision and mobile photography (Sep. 04, 2014)
  The sensor pixel size is rapidly approaching the wavelength of light, leaving limited opportunity to reduce costs by further shrinking pixels, the fundamental building block of the image sensor. In addition, the increasing performance requirements of video and vision provide challenges for mobile phones and embedded solutions that are also being called upon to run more and more applications. This article looks at some of the emerging silicon architectures in the form of optimized and innovative processors and sensors that are enabling these advanced features.
  
  
• A Realtime 1080P30 H.264 Encoder System on a Zynq Device (Sep. 01, 2014)
  The Zynq all programmable System On a Chip is a recently introduced device from Xilinx which incorporates two ARM A9 CPU cores, I/O peripherals, memory controller, and programmable logic. This paper describes the implementation of a 1080P30 realtime H.264 encoder system on the device.
  
  
• BIST schemes for ADCs (Aug. 29, 2014)
  A commonly encountered analogue circuit is the analog to digital converter (ADC), and in this paper we will discuss the conventional method of testing ADCs, as well as the various built-in self-test schemes that can be used for their testing.
  
  
• GC Nano - User Interface (UI) Acceleration (Aug. 11, 2014)
  Crisp, clear, and responsive user interface HMI (human machine interface) has become equally important to the user experience as the content or the device form factor. A beautifully crafted smartphone that uses a combination of brushed titanium and smudge-proof glass may look great in the hand, but the user will quickly opt for another product if the user interface stutters or the screen is hard to read because of aliased and inconsistent fonts. The same scenario also applies to HMI in wearables and IoT devices, which is the focus of this white paper.
  
  
• Deliver at 100G: The impact of smart memory (Jul. 30, 2014)
  Middleware and full function appliance box design teams face the daunting challenge of developing and meeting the performance requirements for next generation 100Gbps. Using general-purpose multi-core CPU arrays provides the flexibility needed to support emerging trends like SDN and NFV. However the packet inspection and buffering functions point to the need to direct traffic to achieve load-balanced cores.
  
  
• MBIST verification: Best practices & challenges (Jul. 28, 2014)
  Embedded memories are an indispensable part of any deep submicron System on a Chip (SoC). The requirement arises not only to validate the digital logic against manufacturing defects but also do robust testing of large memory blocks post-manufacturing.
  
  
• Designing optimal wireless base station MIMO antennae: Part 2 - A maximum likelihood receiver (Jul. 23, 2014)
  In MIMO antenna design, the maximum likelihood (ML) receiver has significant advantages, but these come at the price of implementation complexity.
  
  
• Challenges in LBIST validation for high reliability SoCs (Jul. 22, 2014)
  Logic built-in self test (LBIST) is being used in SoCs for increasing safety and to provide a self-testing capability. LBIST design works on the principle of STUMPS architecture. STUMPS is a nested acronym, standing for Self-Test Using MISR (Multiple Input Signature Register) and Parallel SRSG (Shift Register Sequence Generator).
  
  
• Is Your Processor IP ISO 26262-Compliant? (Jul. 22, 2014)
  At every level in the development of safety systems, from the selection of processor IP and the IP development process, to software development and even document creation, there is a need to address functional safety compliance. Understanding the compliance with ISO 26262 from a processor IP perspective, the role of the processor IP, its software, and its documentation can help ease the certification process.
  
  
• Designing optimal wireless basestation MIMO antennae: Part 1 - Sorting out the confusion (Jul. 21, 2014)
  This article will first review the relevant MIMO modes and technology and the advantages of choosing a suboptimal MLD receiver over a minimal mean square error (MMSE) receiver. It will also explain the complexities of the MLD implementation and how to resolve them using suboptimal ML solutions.
  
  
• Validating and using the I2C protocol (Jul. 17, 2014)
  I2C is a two wire, clock synchronized protocol with a bi directional data line and a uni directional clock line. Its simplicity lies in its use of only two lines for communication and its complexity lies in the fact that these lines are shared among all the devices on the bus. The I2C bus can have several masters and slaves connected on the same two lines and bus arbitration is employed to handle bus contentions. The scope of this article is to bring out some common I2C issues that come up while validating and using the I2C protocol.
  
  
• Reduce SoC verification time through reuse in pre-silicon validation (Jul. 11, 2014)
  A key focus of the IC design industry is to deliver first-pass silicon, which means finding most, if not all, of the potential defects before tape-out. This is extremely difficult due to increasing design complexity, clock speeds, multi-layered software, and shrinking technology and cycle time. Each re-spin of the silicon may cost a company millions of dollars and a lot of wasted time and effort. With more and more third party IP being used in the SoC to shorten time-to-market, the task of finding bugs before silicon becomes more difficult due to limited knowledge of the external IP by the SoC engineers.
  
  
• Define Analog Sensor Interfaces In IoT SoCs (Jul. 03, 2014)
  Also known as “smart everything,” the Internet of Things (IoT) is grabbing headlines across the industry. As any great new technology, it comes wrapped in shiny paper that touts it as the solution for all things connected, be it the online tracking of the merchandise in a truck across the continent, the automatic sensing of the color of toast in the toaster, or measuring the number of steps walked in a day.
  
  
• Guide to Choosing the Best LDO for Your Application (Jun. 23, 2014)
  LDOs are so common inside portable devices, state of the art power management integrated circuits (PMICs) for smartphones and other portable devices include over a dozen LDOs. To know which LDO you need, you must first define the application of your LDO and then examine which parameters are most important when dealing with that application. With so many different LDO applications and the multiple parameters that characterize a particular LDO, it is not easy to determine which LDO is best suited. To help you figure this out, we have put together this reference. This guide presents a comprehensive list of all of the different LDO parameters with definitions, the most common applications of LDOs, and which parameters are critical for each.
  
  
• Application Architectures for FPGA-Based Image Processing (Jun. 20, 2014)
  Video and imaging circuitry only changes one way. Higher resolution, higher frame rates, and lower power requirements (particularly for UAV applications) equates to higher capacity and complexity. This is driving some software developers to sample the technique of offloading processor functions to run in parallel in field programmable gate arrays (FPGA).
  
  
• Sensor fusion enables sophisticated next-gen applications (Jun. 10, 2014)
  In this Product How-To article Rich Collins of Synopsys describes the importance of sensor fusion in connected embedded systems and how the company’s ARC EM4 32-bit CPU-based sensor IP Subsystem allows design of devices with the right performance/power consumption mix.
  
  
• Conquering the challenges of PCIe with NVMe in order to deliver highly competitive Enterprise PCIe SSD (Jun. 09, 2014)
  To help leading storage companies address the booming demand of PCI SSD (Solid State Drive), PLDA enhances the end-to-end data integrity functionality of its PCIe soft IP products and showcases a NVMe demo on its hardware.
  
  
• Low Power Analysis and Verification of Super Speed Inter-Chip (SSIC) IP (Jun. 02, 2014)
  In our current work, we focus on the low power analysis and verification challenges and the methodology used to verify low power design. The power-gating feature that we term Hibernation brings in significant power savings to Synopsys SSIC IP Controller. The verification tests the functionality of the Controller before, during and after hibernation state. The low power analysis will showcase the power savings achieved in SSIC IP with and Without Hibernation.
  
  
• Overcoming advanced SoC routing congestion with 2.5D system in packaging (May. 19, 2014)
  The use of a 2.5D system to integrate basic SoC functional blocks can eliminate much of the routing congestion that results when sending signals back and forth between cooperating elements.
  
  
• Performance optimization using smart memory controllers, Part 1 (May. 19, 2014)
  In this article, we explain how a smart memory controller can improve the performance of a system. We discuss various issues in an SoC and describe features of a smart memory controller that can be configured to mitigate these issues.
  
  
• Tradeoffs of LDO Architectures and the Advantages of Advanced Architecture "Capless" LDOs (May. 12, 2014)
  Power management of battery-powered electronic devices is becoming increasingly more important for the present and future microelectronics industry. This application note details the difference between low dropout (LDO) voltage regulators that use output capacitance and those that do not and how your system designs can benefit from or be improved by not using an output capacitor.
  
  
• An alternative to ADC, power and RF IC hardware: the S3 Group (May. 05, 2014)
  I was initially attracted to the levels of performance of a recently developed 12 bit SAR ADC (Part # S3ADS160M12BSM40LL) by the S3 Group. This small, very efficient, high-speed SAR ADC performs at 160 Msps at less than 31 fJ energy efficiency. I have been in the semiconductor industry for 26 years and this Energy Efficiency spec is new to me. I had never seen it on a datasheet.