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IP / SOC Products Articles

• Auto Clock Generation in a SoC (May. 05, 2014)
  This paper discusses a novel idea on automatic clocks generation for a SoC. A standard configurable input file has all the required clock requirements in a SoC given by the designer. A scripting language is used to parse the input file. The script generates Synthesizable System Verilog RTL, System Verilog Assertions, Clock Constraints and Documentation in HTML format.
  
  
• Protecting multicore designs without compromising performance (Apr. 28, 2014)
  As data rates climb and malicious software attacks escalate, traditional approaches to security will be replaced by integrating such protection directly into the multicore-based Intelligent Packet Engine hardware IP.
  
  
• Adding CRC to BIST improves SoC safety & reliability (Apr. 28, 2014)
  Implementation guidelines for including CRC in SoC BIST controllers, automotive or otherwise.
  
  
• Behavioral Model of a DDR Memory Controller in a DFi - Frequency Ratio System (Apr. 21, 2014)
  The paper details the DDR MC Phase encoding algorithm in a DFi™ frequency ratio system. It is intended for a technical audience interested in learning about how the DDR MC encodes the PHY timing information in the Phase- Specific bus. Please refer to the DFi™ 3.1 specification for complete details on frequency ratio systems.
  
  
• Implementing a Design Management System (Apr. 17, 2014)
  I recently had lunch with a dejected engineer from a semiconductor startup in big trouble. After months of effort at no small expense, the chip design project was an utter failure, though not a result of the chip’s poor power, performance or area numbers. It was worse than that –– almost everything went wrong, from resource management, schedule slips and budget to feature creep and mismatched expectations.
  
  
• Scaling the 100 GbE Memory Wall (Apr. 14, 2014)
  All interrelated system-level tradeoffs, including performance, pin count, and area, ultimately are driven by power consumption considerations. At 100 and 400 GbE, network chip vendors must consider end-to-end solutions for equipment OEMs. To remain competitive, OEMs plan to introduce multi-terabit systems that aggregate multiple 100 Gbit/s ports on each line card.
  
  
• On-Chip Interconnect Costs Spawn Research (Mar. 27, 2014)
  With 16nm chips moving to production this year, companies are actively developing the 10nm and 7nm technology nodes. These generations are interconnect heavy -- more than 50% of their cost is due to the back-end-of-line (BEOL) wiring levels, and designs are dominated by interconnect delay.
  
  
• SoC interconnect architecture considerations (Mar. 25, 2014)
  The SoC interconnect architecture has a huge impact on what a given SoC can deliver. This is a huge topic of interest for the SoC designers. This is hardly surprising, with the SoC designs nowadays getting more and more communication-centric. Most of the SoCs nowadays consist of multiple processors, hardware accelerators for specific tasks, on chip memories, several standard interfaces to connect to real world devices and custom Intellectual Property (IP) blocks.
  
  
• Challenges associated with Digital-Analog combined IP's (Mar. 13, 2014)
  With the increase in complexity and the content of these Analog blocks, there is an enhanced focus to move more and more functionality, wherever possible, into the Digital domain which allows faster modifications, easy reuse and portability across technology nodes. Having said that there are inherent challenges associated with such Digital-Analog combined IP’s, referred to as Mixed Signal IP’s hereafter, both in Design and Verification in order to robustly signoff such IP’s at block verification level for integration in any SoC.
  
  
• Forward-Looking SoC-based PHY Architecture for Macro and Small Cell LTE eNode-Bs (Mar. 10, 2014)
  This paper describes an efficient, forward-looking architecture that enables handling of various form factors of LTE base stations with minimal software modification and without architecture changes. The architecture proposed allows easy migration to the next generation SoCs as well as to more powerful SoCs of the same generation. Our implementation of this architecture has now migrated two generations of SoCs for LTE Release 9 small and macro cells, and is ready for migration to a multi-sector, LTE-A macro base station.
  
  
• Understanding sigma delta ADCs: A non-mathematical approach (Mar. 06, 2014)
  In this paper, we will attempt to explain sigma delta converters with a non-mathematical approach, covering the basic concepts of noise shaping and oversampling, explained with the help of some examples. These concepts along with digital decimation filters are later incorporated together to reveal the magic behind sigma delta converters. This paper also covers the basics of first and second order sigma delta ADCs and how the order of the sigma delta modulator impacts the performance of the ADC.
  
  
• Smaller scale chip design relies on creative thinking and collaborative workflow (Mar. 05, 2014)
  Chip design can be a complex and time consuming endeavor that demands accuracy and speed. While larger enterprises have the wherewithal to invest in sophisticated EDA (electronic design automation) tools for development and verification, smaller research facilities within rapidly growing tech companies have to rely on a disciplined, integrated team approach to development.
  
  
• Scalable Architectures for Analog IP on Advanced Process Nodes (Mar. 03, 2014)
  This paper elaborates on how ADCs can work with Moore's Law to move with the power and area scaling trends that are common for digital circuits. It will compare the main ADC architectures and conclude that the Successive-Approximation Register (SAR) based ADC is very well positioned as the architecture of choice for medium- and high-speed ADCs in modern SoCs, especially in 28-nm processes and beyond. It will describe implementations of the SAR ADC architecture that reduce power consumption and area usage dramatically, enabling SoC designers to successfully integrate these analog components in their next SoCs.
  
  
• The hardware (and software) implications of endianness (Mar. 03, 2014)
  Today’s SoCs integrate many hardware IP blocks; designers need to be aware of the order of bytes on the byte lanes of connecting buses when transferring data. In a system with several discrete hardware components - such as a host processor and external devices connected to it via a PCI bus, for example - the hardware components may support different endianness modes. Device driver developers need to make the data transfers among these hardware components endianness-proof.
  
  
• Next Generation Wireless IP for the Internet of Things (Feb. 24, 2014)
  Most embedded systems today use some form of wireless connectivity. Specifically, the Internet of Things would not be possible without wireless interfaces. There are many considerations in the integration of wireless connectivity into the core system-on-chip around which systems are built. This paper provides a perspective on the integration of wireless connectivity subsystems within the system-on-chip (SoC).
  
  
• RRAM: A New Approach to Embedded Memory (Feb. 11, 2014)
  The emergence of the Internet of Things (IoT) and the insatiable demand for smart devices in every aspect of life is driving a complete overhaul of traditional wisdom in the microcontroller and embedded memory markets.
  
  
• Design Tip: Implementing an SoC with dependable 50% duty cycles (Jan. 27, 2014)
  This article describes a new approach to implementing clock dividers in a system-on-chip design that supports both high performance and low power. It uses a dual edge counter-based configurable frequency divider that can not only divide the clock frequency for both even and odd configurable division factors, but at the same time maintains a 50% duty cycle of the output divided clock.
  
  
• PCIe and storage devices get connected (Jan. 20, 2014)
  SSDs (solid-state drives) are rapidly becoming the storage method of choice. With this changing of the guard from hard-disk drives to SSDs, there is a need for different connections than are used for hard drives or peripherals to utilize the an SSD's full potential. The connector and protocols discussed here are the future for the storage industry.
  
  
• Using USB 3.1's Multiple INs To Reach 10 Gbps Data Rates (Jan. 16, 2014)
  When working with USB 3.1, designers are challenged to provide the 10 Gbps USB 3.1 speeds that customers expect while supporting backward compatibility with USB 3.0 devices in a hub topology.Using multiple INs provides a greater level of flexibility to the system.
  
  
• Overcome memory-imposed access rate and bandwidth constraints (Jan. 13, 2014)
  Design teams building high-speed, next-generation network communications equipment suffer under the constraints imposed by memory. Some design solutions use only on-chip memory which is inherently limited in capacity and competes with silicon area that could be otherwise used for computation or other functionality. More complex applications require external memory and at the processing rates available today need the highest possible random access rate to that memory. Traditional memory interfaces are a burden to performance because they are plagued by slow speeds, lengthy latency, and high pin counts. As a result, conventional design approaches to implementing external memory have already reached the point of diminishing returns.
  
  
• Moving PCI Express to Mobile (M-PCIe) (Jan. 06, 2014)
  This paper will begin with a quick overview of the specification and its application space, and then go into details such as bandwidth and clocking considerations, PHY interface differences, power management impacts, and the tradeoffs related to choices around link-layer changes. These changes may impact the transaction and application layers of devices moving from PCIe to M-PCIe, and the paper will detail those issues. A basic understanding of PCI Express concepts is helpful but not required.
  
  
• Shaving power/area with merged logic in SoC designs (Jan. 02, 2014)
  In the modern era, there is always a requirement to achieve high frequency with lower power consumption. Achieving both targets simultaneously is very difficult and the situation becomes even more complex while moving down the technology nodes due to various sub-micron effects
  
  
• Optimizing Sensor Performance with 1T-OTP Trimming (Dec. 30, 2013)
  A sensor is a device that detects a change in a stimulus and converts it into an electronic signal that can be measured or recorded. The stimulus can be many things, including a physical property, environmental parameter, chemical composition or a location, to name just a few. All sensing elements have nonlinearities that include an intrinsic nonlinearity over sensing range along with offset and sensitivity nonlinearity variations over temperature.
  
  
• Portable and scalable solution for off-screen video frame composition and decomposition using OpenGL ES (Dec. 30, 2013)
  One of the most essential software components in multimedia applications like video communication, video networking, video security etc., is a video frame composition and decomposition module for off-screen surfaces. Off-screen surfaces are those video frames which are not displayed on the screen.
  
  
• The growing role of analog-digital on-chip integration in saving energy (Dec. 16, 2013)
  Mixed-signal silicon design, bringing the worlds of analog and digital technology onto a single die, has never been an easy task. Formerly, the analog and digital teams would work independently on their designs, leaving the place and route team with the thankless task of integrating everything onto a single chip. A microcontroller design, with all of its carefully thought out peripherals, would be routed leaving analog-sized holes for the oscillator, ADC and transceivers needed to complete the design.
  
  
• Mixed Signal Design & Verification Methodology for Complex SoCs (Dec. 16, 2013)
  This paper describes the design & verification methodology used on a recent large mixed signal System on a Chip (SoCs) which contained radio frequency (RF), analog, mixed-signal and digital blocks on one chip. We combine a top-down functional approach, based on early system-level modelling, with a bottom-up performance approach based on transistor level simulations, in an agile development methodology. We look at how real valued modelling, using the Verilog-AMS wire that carries a real value (wreal) data type, achieves shorter simulation times in large SoCs with high frequency RF sections, low bandwidth analogue base-band sections and appreciable digital functionality including filtering and calibration blocks.
  
  
• Why There's No Need to Fear JESD204B (Dec. 12, 2013)
  A new converter interface is steadily picking up steam and looks to become the protocol of choice for future converters. This new interface, JESD204, was originally rolled out several years ago, but it has undergone revisions that are making it a much more attractive and efficient converter interface.
  
  
• Understanding - and Reducing - Latency in Video Compression Systems (Dec. 02, 2013)
  In the video world, latency is the amount of time between the instant a frame is captured and the instant that frame is displayed. Low latency is a design goal for any system where there is real-time interaction with the video content, such as video conferencing or drone piloting. But the meaning of “low latency” can vary, and the methods for achieving low latency aren’t always obvious. Here we’ll define and explain the basics of video latency, and discuss how one of the biggest impacts in reducing latency comes from choosing the right video encoding.
  
  
• Development of a 4K 10-Bits HEVC Encoder (Nov. 25, 2013)
  The new High Efficiency Video Coding (HEVC) video compression standard results from the work of the latest joint project of the ISO/IEC Moving Picture Experts Group (MPEG) and ITU-T Video Coding Experts Group (VCEG) standardization groups, performed under the name of the Joint Collaborative Team on Video Coding (JCT-VC) (ITU-T and ISO/IEC).
  
  
• Optimizing High Performance CPUs, GPUs and DSPs? Use logic and memory IP - Part II (Nov. 21, 2013)
  In Part I of this two-article series we described how the combination of logic libraries and embedded memories within an EDA design flow can be used to optimize area in CPU, GPU or DSP cores. In Part II we explore methods by which logic libraries and embedded memories can be used to optimize performance and power consumption in these processor cores.