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IP / SOC Products Articles

• Low Power Design for Testability (Jun. 17, 2013)
  Design for testability (DFT) and low power issues are very much related with each other. In this paper power reduction methodologies are discussed for a given design. Power management circuitries are developed to reduce functional power of the design. Power aware Scan Chains are implemented to create test environment which result into reduction in test power. Design for testability is applied to test power management circuits using Power Test Access Mechanism. Also few methods are discussed to implement DFT to test power management circuitry and improve test and fault coverage during ATPG.
  
  
• Scaling NAND flash to 20-nm node and beyond (Jun. 11, 2013)
  Intel-Micron have recently introduced a scalable planar NAND cell for the 20nm technology [1]. Replacement of conventional wrap floating gate (FG) NAND memory cell with a High-K/Metal gate planar cell that can scale to the 20nm node and beyond was a significant challenge and required comprehensive material and cell exploration and optimization. This paper discusses some of the fundamental cell design issues considered and addressed to arrive at this planar cell technology including the reasoning behind choosing the planar floating gate cell over the nano-crystal cell, and the nitride cell.
  
  
• Using non-volatile memory IP in system on chip designs (Jun. 11, 2013)
  While unlimited re-programmability might be seen as an advantage during software development, once the device is shipped it becomes a product’s greatest vulnerability...
  
  
• Soft memories in PD flow : Myth and Reality (May. 28, 2013)
  Even though soft memories or fifos make life easy for the rtl designer it may create issues in different stages of the PD flow under specific circumstances. We will discuss these issues in detail and we will see how this can be handled at the PD end.
  
  
• How to use ECC to protect embedded memories (May. 27, 2013)
  In this article we discuss transient error detection and correction methods using advanced error correction code (ECC) based solutions for embedded memories in order to meet the requirements of today’s high-reliability applications.
  
  
• Address jitter and noise more effectively with DDR4, part1 (May. 22, 2013)
  The latest generation of DDR memory, DDR4, doubles the speed of the current generation of DRAMs, DDR3, with end-of-life data rates of 3.2 GT/s. Compared to the first generation of DDR memory, which started out at 200 MT/s, DDR4 will be running almost 16 times faster.
  
  
• Generic DDR Behavioural Model (May. 20, 2013)
  This paper represents a generic executable architecture. It represents the efficient behaviour of the Memory Model to be used for verification of SOC communicating with DDR SDRAMs or can be used as the third party Model verification (passive element). Paper shows the capability as standalone VIP architecture and also represents the market value of DDR model in the present technical era with different technical views and challenges faced. It also givessolution of supporting different part number of established DDR vendors like Micron, Elpida, Samsung etc.
  
  
• Design planning for large SoC implementation at 40nm: Guaranteeing predictable schedule and first-pass silicon success (May. 20, 2013)
  Modern SoC development requires a holistic approach and thorough planning starting at the design architecture of the SoC. The ASIC implementation process has to keep pace with the design complexity, performance, and time-to-market, all while ensuring first-time silicon success.
  
  
• How small vendors compete in analog IC market (May. 02, 2013)
  Can a small fabless analog vendor compete with the top five analog IC vendors in global markets? This question is being asked often, especially in the context of emerging Chinese end-system OEMs. Europe used to have many small analog IC specialists – most but not all have by now been acquired. In this case study, we will compare one such small but well-established company competing with the world’s largest analog company.
  
  
• Intellectual property security: A challenge for embedded systems developers (Apr. 29, 2013)
  A company’s success - and its future - depends on the creation and successful defense of intellectual property (IP), which is generally defined as "creations of the mind for which exclusive rights are recognized.” IP is the outcome of innovation and work done by an organization/person and gives a company's products an edge over competitors.
  
  
• Using audio codecs IP as the digital audio hub in mobile multimedia systems (Apr. 24, 2013)
  By integrating an audio analog codec that implements the 'audio hub' functionality and is able to process and mix audio signals from asynchronous sources, system designers can free the scarce main processor resources for more relevant tasks and simplify the system design, thus achieving a more effective solution.
  
  
• A Low Complexity Parallel Architecture of Turbo Decoder Based on QPP Interleaver for 3GPP-LTE/LTE-A (Apr. 22, 2013)
  This paper propose an improved method called the modified warm-up-free parallel window(PW) MAP decoding schemes to implement highly-parallel Turbo decoder architecture based on the QPP(Quadratic Polynomial Permutation) interleaver of 3GPP LTE/LTE-A standards.
  
  
• Demystifying the PLL (Apr. 02, 2013)
  When designing a digital communications system on a mixed-signal chip, digital designers tend to avoid PLLs because of their inherent analog nature, and analog designers stay away from them because IDEs involve coding. This article presents a different way of designing a simple PLL.
  
  
• How a MicroBlaze can peaceably coexist with the Zynq SoC (Mar. 28, 2013)
  The Xilinx Zynq-7000 All Programmable SoC already has plenty of processing power onboard. But the presence of powerful twin Cortex-A9 processors and associated peripherals in Zynq's application processing unit (APU) should not keep you from adding one or more MicroBlaze processors in the same package, if your application would benefit from them.
  
  
• Introduction to OpenVG for embedded 2D graphics applications (Mar. 28, 2013)
  OpenVG is an API designed for hardware-accelerated 2D vector graphics. It was designed to help manufacturers create more attractive user interfaces by offloading computationally intensive graphics processing from the CPU onto a GPU to save energy.
  
  
• Using parallel FFT for multi-gigahertz FPGA signal processing (Mar. 28, 2013)
  High-speed fast Fourier transform (FFT) cores are an essential requirement for any real-time spectral-monitoring system. As the demand for monitoring bandwidth grows in pace with the proliferation of wireless devices in different parts of the spectrum, these systems must convert time-domain to frequency-domain ever more rapidly, necessitating faster FFT operations.
  
  
• Communication centric test and debug infrastructure for multi core SoC (Mar. 25, 2013)
  A communication centric SoC debug approach using control transactions, as an extension of the traditional, processor based debug access and control is presented in this paper. A structured approach is presented to control both the processor core and other critical hardware units in a hardware synchronized manner, thereby enabling both synchronous stop and start during a debug session. An efficient and processor independent mechanism to have explicit control the system at run time is presented.
  
  
• Share with PCI Express (Mar. 25, 2013)
  As kids we were taught that sharing is good. The semiconductor industry seems to have forgotten the spirit of that lesson, but one technology that reminds us of what our parents taught us is PCI Express (PCIe).
  
  
• How FPGAs are breathing new life into the analog video format (Mar. 21, 2013)
  Digital video broadcasting, video compression, and ever expanding video resolutions such as 4k x 2k dominate the news in electronics magazines. Yet that little yellow RCA connector remains ubiquitous and large numbers of people still rely on NTSC or PAL analog broadcasting for their viewing pleasure. This article looks at how FPGAs are breathing new life into this presumed dead format.
  
  
• Why migrate to DDR4? (Mar. 13, 2013)
  A knowledge gap exists between the presentation of the technical details in JESD79-4 and understanding the underlying motivations and rationale that led to the standard. In an attempt to bridge that knowledge gap, let’s explain some of the purpose of the DDR4 SDRAM device, and frame it in the context of system level trends.[
  
  
• Design Transition from Sync to Async: Design and Verification Challenges (Mar. 11, 2013)
  This article deals with various challenges faced in modifying a synchronous design to an asynchronous one. It aims to provide a brief overview of design and verification aspects to consider while making this transition.
  
  
• Optimizing clock tree distribution in SoCs with multiple clock sinks (Mar. 11, 2013)
  In this article we describe a structure and a method for propagating clock signals to a multiplicity of clock sink nets in a system-on-chip (SoC) design. We include an improved buffering and wiring apparatus that allows reduction of the number of clock stages, the overall latency, the clock skew, and uncertainty.
  
  
• Building a security-optimized embedded design using protected key storage (Mar. 08, 2013)
  In this Product How-To article, Todd Whitford and Kerry Maletsky of Atmel Corporation describe the many ways in which the security of an embedded microcontroller design can be compromised and how to use the company’s ATSHA204 authentication device to protect critical system IP.
  
  
• "So, when will you be done with your design?" (Mar. 07, 2013)
  Not exactly the question a typical design engineer is looking forward to. You’re at the start of a new project and it is time to commit to a development schedule. Now what? Your first instinct is to be vague. Use verbs like “should” and “hope” and lots of conditional statements. But you know that’s not going to fly. You can give your best estimate. But you’re usually too optimistic and then you will get yelled at when you don’t meet that commitment.
  
  
• Long live the battery! (Mar. 04, 2013)
  There are many factors that affect the device’s power efficiency, which can be expressed in the number of hours between battery charges. Today, in the era of HD mobile screens there are two major issues that contribute to high battery drain – display brightness and power dissipation in the video and graphics subsystem. In this paper we will discuss the latter one – smart video and display pipeline in the System-on-Chip. Smart, which means providing similar performance to competitive solutions, but requiring much less power.
  
  
• Understand and perform testing for MIPI M-PHY compliance (Feb. 19, 2013)
  As MIPI Alliance standards gain increasing acceptance in the world of mobile device design, engineers need to become proficient at electrical PHY layer compliance testing for the higher speed M-PHY serial interconnects. A full set of tests spanning both the transmitter and the receiver are required to validate designs – a task that is made tougher as speeds and complexity increase. Understanding how to setup and perform critical verification and debug tests is critical to any successful M-PHY development effort.
  
  
• Designing low-power video image stabilization IP for FPGAs (Feb. 19, 2013)
  Image stabilization is an important capability for many electro-optic sensors, where an operator or user is required to view the output imagery. The technique can therefore enhance many practical viewing systems, spanning a very broad range of applications including those found in defense and security sectors.
  
  
• Silicon-Accurate Fractional-N PLL Design (Feb. 18, 2013)
  Fractional-N PLLs are a useful class of PLLs and not well understood. This paper explains in simple terms how these differ from a regular integer PLL. Common applications are listed along with a brief description of the key performance parameter – jitter.
  
  
• Who's managing your power management? (Feb. 12, 2013)
  Today’s complex systems employ a wide variety of semiconductor technologies. From the deepest sub-nanometer processors to the analog I/O, it’s easy to see the need for power management devices for multiple voltages – 1.0V, 1.2V, 1.5V, 1.8V, 2.2V, 2.5V, 2.8V, 3.0V, 3.3V and more – all in the same box.
  
  
• Implementing analog functions in rugged, rad-hard FPGAs (Feb. 12, 2013)
  FPGAs have already changed the cost/reliability paradigm for embedded systems in high-reliability applications, thanks to advances in hardness and power reduction. But on many embedded applications for high-reliability markets, designers depend on a number of peripheral analog components such as analog-to-digital and digital-to-analog converters to talk to the real world.