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IP / SOC Products Articles

• Configurable dividers for SOC / block-level clocking (Sep. 04, 2012)
  This article illustrates various implementations of configurable clock divider logic used in SOCs today and highlights their challenges, advantages or limitations over the others.
  
  
• Physical Attacks against Cryptographic Implementations (Sep. 04, 2012)
  Since the advent of side channel attacks, classical cryptanalysis is no longer sufficient to ensure the security of cryptographic algorithms. In practice, the implementation of algorithms on electronic devices is a potential source of leakage that an attacker can use to completely break a system. The injection of faults during the execution of cryptographic algorithm is considered as an intrusive side channel method because secret information may leak from malicious modifications of the device's behavior.
  
  
• Performance is marred by memory (Aug. 31, 2012)
  For many years the industry created faster and faster processors. This was possible because more transistors were available in each technology node that could be used to produce even more complex and optimized pipelines.
  
  
• Proposal of a Dynamically Reconfigurable Processor Architecture with Multi-Accelerator (Aug. 20, 2012)
  In this paper, we propose a dynamically reconfigurable processor architecture with a multi-accelerator using Dynamic Partial Reconfiguration (DPR) technology by XILINX. The proposed architecture consists of a processor, some memories, some buses, controllers and some dynamically reconfigurable accelerators. We employ a multi-bus system and design the controllers for a dynamically reconfiguration. A JPEG encoder and decoder that are open-source IPs are used as target applications. The proposed architecture is implemented on a Virtex-6 FPGA and evaluated regarding the circuit size and reconfiguration time. The results showed that the partial reconfiguration time was small enough.
  
  
• Growing audio requirements in SoCs (Aug. 08, 2012)
  As consumer devices such as tablets, media players and home theater systems continue to incorporate more audio functionality, the systems on chip (SoCs) designed for these devices become more complex. These SoCs must support a growing list of audio requirements such as a wider range of high-definition audio compression formats, multi-channel audio content, higher sampling rates and advanced audio post-processing functions.
  
  
• ASIC Implementation of a Speech Detector IP-Core for Real-Time Speaker Verification (Jul. 23, 2012)
  For voice processing it is important to ensure that the signal to be analyzed actually contains relevant information, especially if the system is operating in a real-time. This paper presents an IPcore speech detector for real-time systems, focusing on identification of segments of silence or voice, used in pre-processing of input signals to Speaker Recognition and Verification Systems. The IP-core was designed to be able to be adapted to different environments of use and based on energy of samples to classify them as voice or silence.
  
  
• OEM Custom Solutions - BOM Cost Reduction (Jul. 23, 2012)
  As process technology nodes advance, falling costs & increasing capacity on older nodes enable OEMs embark on custom ASIC developments to take advantage of higher levels of integration thereby realizing significant BOM savings. Never before have mixed signal ASIC developments been within reach of so many, lower volume applications. Choosing the right partner to realize the silicon development, in a cost effective and low risk manner, is still a challenge to be overcome by OEMs.
  
  
• Using code-coverage analysis to verify 2D graphic engines in automotive apps (Jul. 23, 2012)
  High-resolution graphics displays are becoming a key part of automotive manufacturers' strategies to simultaneously differentiate from their competitors, reduce production cost, and increase customer satisfaction. Our group at Fujitsu develops IP blocks and SoCs to help customers realize these advantages.
  
  
• FRAMs as alternatives to flash memory in embedded designs (Jul. 19, 2012)
  In recent years, integrated circuit manufacturers have been considering FRAM as a strong contender for embedded, non-volatile memory, as an alternative to flash technology. This article discusses key technology attributes of FRAM while exploring specific use cases that demonstrate FRAM’s advantages.
  
  
• Design of a 8051 Microcontroller in FPGA with reconfigurable instruction set (Jul. 16, 2012)
  This paper describes the design and implementation of a version of the 8051 microcontroller, one of the most commercially used microcontrollers in FPGA with reconfigurable instruction set.
  
  
• Revisiting the analogue video decoder: Brushing up on your comb filters (Jul. 12, 2012)
  With such a large number of video decoders in the market it might seem an unnecessary indulgence to spend time looking again at the design of this fundamental but apparently obsolete building block, and certainly new designs are not appearing on the market and haven't done so for three or four years.
  
  
• PCIe goes Clockless -- Achieving independent spread-spectrum clocking without SSC isolation (Jul. 09, 2012)
  PCI Express (PCIe) has established itself as the IO interconnect of choice for communication within the server and PC environment. Today, an emerging trend among designers is extending PCIe beyond the PC/server while maintaining the advantages of simplicity, bandwidth, scalability, low power and cost. One of the major system-level challenges in extending PCIe outside the box has been clock distribution between separated domains.
  
  
• Anti-fuse memory provides robust, secure NVM option (Jul. 06, 2012)
  Embedded non-volatile memory (NVM) intellectual property (IP) is a requirement for storing data that must be preserved when power to the chip is removed. NVM is found in almost every system on chip (SoC) design today, especially those targeting connected devices accessing content protected by digital rights management and sensitive financial or personal data. As these SoC designs migrate toward 28 nm and lower processes, engineering teams are re-examining the available commercial options. This reappraisal is occurring because of challenges presented by these smaller geometry processes. Suddenly, what was once an insignificant commodity is threatening to become a technology bottleneck.
  
  
• Understanding DDR SDRAM timing parameters (Jun. 26, 2012)
  Many engineers who have ever dealt with DDR SDRAM must have been intrigued by the various timing parameters of the DRAM. This article explains the various timing parameters and its impact on the performance of the DRAM.
  
  
• Sensor Interface - Analogue Front End Family "From the Real World to the Digital Word" (Jun. 25, 2012)
  Systemcom Ltd. launched the family of chip solutions which can be used for instance with light sensor, to capture light, then to process the information and provide data to the standard controlling unit (electronic device). The product line consists of silicon proven, so called IP ("Intellectual Property") modules, as the components of the sensor interface - Analogue Front End (AFE) family. It can be really said that such chip solutions make connection from the real world to the digital word.
  
  
• Debunking 10GBase-T Myths (Jun. 11, 2012)
  While it may be true that good things come to those who wait, too much waiting can lead to uncertainty. Take 10GBase-T networking products, for example. The 10GBase-T standard published almost six years ago and the long wait for network gear has provided fodder for the digital rumor mill to churn.
  
  
• Smart SoCs drive 3G-to-4G transition (Jun. 05, 2012)
  The solution for delivering today’s escalating broadband mobile network traffic is to deploy many more basestations, closer to the user. To accomplish this, the Long-Term Evolution (LTE) standard includes the concept of the multiradio-access-technology heterogeneous network (multi-RAT HetNet), which combines big, traditional basestations with small cells.
  
  
• Data-in-transit Protection for Application Processors (Jun. 04, 2012)
  This whitepaper attempts to help designers tasked with building an Application Processor based system that needs to incorporate support for what is typically called 'Data in Transit Protection'.
  
  
• Designing embedded SoCs using older resistive technologies (May. 31, 2012)
  When designing an SoC with a generic 32-bit MCU based on 0.18um (180 nm) processes with flash and a rich suite of analog and digital IPs, the authors found that the pre-route engines from current EDA tool vendors are tuned for smaller transistor node sizes and are not very good at the larger 180 nm geometries. Here are the steps they took to overcome such problems.
  
  
• A scalable, cost-effective phase change RAM technology (May. 22, 2012)
  We successfully developed highly scalable and cost-effective PCRAM technology based on 0.007 µm2 (4F2, 84-nm pitch) sized novel cell scheme. The chip size and density are 33.207-mm2 and 1 Gb. The device functionality and reliability were clearly demonstrated through fully integrated chip, which showed a promising feasibility for productive NVM applications.
  
  
• 3D IC 2-tier 16PE Multiprocessor with 3D NoC Architecture Based on Tezzaron Technology (May. 14, 2012)
  In this paper, we describe the design flow, architecture and implementation of our 3D multiprocessor with NoC. The design based on 16 processors communicating using a 4x2x2 mesh NoC spread on two tiers is discussed in detail and will be fabricated using Tezzaron technology with 130 nm Global Foundaries low power standard library. The purpose of this work is to accurately measure NoC performances in real 3D chip when running mobile multimedia applications to evaluate the impact of 3D architecture compared to 2D.
  
  
• How to use the CORDIC algorithm in your FPGA design (May. 14, 2012)
  Most engineers tasked with implementing a mathematical function such as sine, cosine or square root within an FPGA may initially think of doing so by means of a lookup table, possibly combined with linear interpolation or a power series if multipliers are available. However, in cases like this the CORDIC algorithm is one of the most important tools in your arsenal, albeit one that few engineers are aware of.
  
  
• Channel Core Flex: An Advanced Channeliser for Next Generation Digital Radio Receivers (May. 07, 2012)
  This paper discusses the relative merits of the various digital signal processing techniques used to channelise signals. ChannelCore Flex (CCF) exploits all of these strengths to provide a flexible channeliser architecture that is capable of supporting thousands of independently defined channels in a single FPGA. The CCF core can be tailored at build-time to support the user’s generic channel plan and required level of flexibility. The precise channel plan can then be loaded and updated at run-time. The FPGA resources required to implement CCF in a Xilinx Spartan-6 LX100 are presented for an example channel plan with 1024 channels of various bandwidths.
  
  
• Processor Optimization Pack (POP) Solutions: Enabling the Fastest Design Closure of Your ARM Cortex-A9 Processor (Apr. 30, 2012)
  This paper discusses the ARM Physical IP Processor Optimization Pack (POP) solution, the main physical IP components, the benchmarking and the techniques that can be used to drive the best possible performance while maintaining energy efficiency through leakage and dynamic power reduction. The paper will focus on key findings from ARM's POP benchmarking activity.
  
  
• Changing the paradigm for TV silicon tuners (Apr. 26, 2012)
  Although the TV market continues to mature, the underlying architectures inside the television continue to evolve to drive down prices. This article will look at key TV market trends and their effect on next-generation TV front-end solutions.
  
  
• The Challenge of the Clock Domain Crossing verification in DO-254 (Apr. 23, 2012)
  In order to meet high-performance and low-power requirements, FPGA and ASIC designs often include many separate clock domains. This practice creates Clock Domain Crossing (CDC), which occurs whenever a signal is transferred from a clock domain to another. However, these signals may cause data corruption issues, only occurring during post-layout verification, because conventional RTL verification techniques cannot detect resynchronization problems. As a consequence, critical bugs may escape the verification process and simulation does not accurately predict asynchronous silicon behavior.
  
  
• DMA IP Integration (Apr. 23, 2012)
  There are many IP’s today . These IP’s can be simple IP’s like Timer to complex IP’s like Accelerators. In Most of the cases IP’s are Integrated in standard way. There are cases where you have the option of Integrating it differently. This goes un-noticed or unable to be implemented due to time constraints. One such IP that would be discussed in this paper is DMA . This paper tries to explain idea of Integrating Direct Memory access(DMA) and Interrupt Control Unit(ICU) differently but final implementation requires some changes in IP. There is a possibility that alternate design explained below may be already implemented.
  
  
• Low power is everywhere (Apr. 19, 2012)
  Meeting power budgets for most System-on-Chip (SoC) designs today is no longer a requirement for mobile applications only. Almost every market segment today has some concern with designing in low power features—although the driving factor for why does differ among them. The primary impetus for low power design was initially driven by the mobile market due to the need for extending battery life; however, different segments do have different reasons for making power a primary design requirement.
  
  
• Enabling High Performance SoCs Through Multi-Die Re-use (Apr. 16, 2012)
  This paper gives a high-level overview of a technique for rapid design of new IC designs using multiple dice packaged in a variety of aggregations allowing for differnent performance levels and price points to be achieved. The technique relies on a new high-bandwidth low pin-count communication channel between two or more dice.
  
  
• Which USB is right for your application? (Part 3) (Apr. 09, 2012)
  In 2007, I wrote a two-part series titled “Which USB is Right for your Application” for Planet Analog (Part 1 and Part 2). Since then, several new and different “versions” of USB have been released. In this article, I discuss how they have been deployed in the market in the almost five years since.