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IP / SOC Products Articles

• Encoding H.264 without External DRAM : Power and Quality Comparison (Apr. 02, 2012)
  This article compares the power consumption and quality of the generated bitstream between two Ocean Logic H.264 encoder cores : OL_H264E that uses external DRAM to store the reference frame store and OL_H264E_CFS that uses a Compressed Frame Store (CFS) technology that does not need external DRAM.
  
  
• Ensuring Successful Third Party Intellectual Property (IP) Integration (Mar. 26, 2012)
  To ensure proper IP core integration, Open-Silicon has developed a detailed and comprehensive process involving close collaboration with IP partners and the SoC design team. This article will illustrate this process by showing how Open-Silicon and Kilopass worked together on a recent project to ensure success.
  
  
• Adjusting and calibrating out offset and gain error in a precision DAC (Mar. 26, 2012)
  This application note describes the DAC errors and their sources, and then describes methods for calibrating out that error in both the analog and digital domains.
  
  
• Building a NAND flash controller with high-level synthesis (Mar. 22, 2012)
  In this article, we describe how we were able to apply a commercial HLS tool (Cadence C-to-Silicon Compiler) to a NAND flash controller with an error correction code (ECC) block. The initial ECC design was based on an ECC software program, which led to a large area due to two large arrays. We then used our domain knowledge of the ECC coding theorem to structure the code for hardware implementation.
  
  
• Integrating audio codecs in next-generation SoCs for smartphones and tablets (Mar. 21, 2012)
  This article presents the test results and discusses the business and technical challenges of integrating audio functionality into a 28-nm mobile multimedia SoC, while also offering insight on how to overcome those challenges. Some key design considerations are also explained, including scaling limitations, supply voltage requirements and system partitioning options.
  
  
• Resistive RAM for next-generation nonvolatile memory (Mar. 13, 2012)
  In this article, we review the main performance figures of hafnium-oxide (HfO2)-based RRAM cells4 from a scalability perspective, outlining their strengths as well as the main challenges ahead.
  
  
• Density Requirements at 28 nm (Mar. 12, 2012)
  In recent discussions with customers around the world, we have been hearing a surprising new message—that, at 28 nm, they have to care about density at the cell design level “like never before.” It’s surprising because density has historically been a manufacturing issue that was handled post tape-out or during chip assembly.
  
  
• Choosing the right synchronous SRAM for your application (Mar. 06, 2012)
  The choice of the right synchronous static random access memory (SRAM) is crucial for networking applications that have increased bandwidth requirements for better system performance. System designers need to be aware of the features and advantages of different synchronous SRAMs technologies to make the right memory selection for their application.
  
  
• Software generated BCH as a way to solve challenges of providing multiple configuration IP (Mar. 05, 2012)
  This article describes the idea of generating synthesizable IP core by a software tool taking an error correction algorithm of BCH (Bose-Chaudhuri-Hocquenghem) as an example. First, it gives an overview on the challenges associated with the error correction module flexibility being a trigger to study the subject. It is followed by a short introduction of NAND Flash memory and Error Correction Codes (ECC) supplemented by BCH algorithm description. In the next chapters specific implementation details are provided accompanied by highlights of configuration parameters and procedure conducted to generate selected architecture of module. Finally, the article concludes giving a very simple example how the application takes full set of parameters and translate it into the RTL source code.
  
  
• Mixed-Signal IP Design Challenges in 28 nm and Beyond (Feb. 27, 2012)
  This paper presents some key concepts necessary to design and build high-quality, mixed-signal IP in 28-nm or smaller geometries. The paper addresses specific design, layout, and verification techniques to address challenges posed in 28-nm technology nodes. Specifically, the paper focuses on three main areas where 28-nm technologies pose some unique challenges, Low-Power Design, Restricted Design Rules, and Design for Yield. Several design examples are presented, highlighting key techniques employed in the Synopsys® DesignWare® Mixed-Signal Intellectual Property portfolio.
  
  
• Clock Domain Crossing Glitch Detection Using Formal Verification (Feb. 13, 2012)
  Current System-on-a-chip (SoC) designs contain increased levels of functional and structural complexities within a single system. With the integration of multiple designs, various clock domains are introduced. In this paper, we present a solution for finding clock domain crossing glitch using a combination of formal verification and static timing analysis techniques. This paper also talks about leveraging a formal verification tool to do sequential equivalence checking between a buggy design and bug fixed design if CDC glitch is found in late design stages
  
  
• DO-254 for Dummies: IP & verification process (Jan. 23, 2012)
  Current electronic development is becoming increasingly dependent on predefined IP blocks (more than 35% of elec-tronic components currently in development use IP). It would be very surprising if the aeronautical industry (as well as other safety critical industries) could do without this key element, which is the only solution that can guarantee time to market and sustainability compatible with current requirements.
  
  
• Leverage Ethernet to improve passenger safety, comfort, and convenience (Jan. 19, 2012)
  As homes become more digitally sophisticated, consumers are developing higher expectations for connectivity and greater levels of safety and comfort in their home away from home—their vehicle. As a result, in-vehicle electronics are growing in number and complexity, keeping step with technology advancements and capitalizing on consumer expectations for a connected driving experience.
  
  
• Smart Engine for Public Key cryptography (Jan. 16, 2012)
  This white paper explains why and how the Smart Engine is ideally applied to Public Key cryptography. It provides more details about the architecture as Baco Silex has implemented it in the BA414E Public Key Crypto Engine
  
  
• AMS and High-speed Interface IP Design Enablement in GLOBALFOUNDRIES 65LPe Process Technology (Jan. 11, 2012)
  Cosmic Circuits has a strong portfolio of over 30 different Analog, mixed-signal and high-speed interface IPs in the GLOBALFOUNDRIES 65LPe technology.
  
  
• Rethinking embedded memory (Jan. 09, 2012)
  It’s no secret that SoC architects have always wanted more on-chip memory. In fact, it’s not uncommon for SoCs to include hundreds of integrated memory cores.
  
  
• Understanding Skew in 100GBASE-R4 applications (Dec. 15, 2011)
  The 100GBASE-R4 physical layer device converts 10-lanes running 10Gbps (CAUI) to 4-lanes running 25Gbps. The conversion process is data agnostic with no provision for rate adaptation, consequently skew management is an integral part of end-to-end system performance.
  
  
• Prototyping Mesh-of-Tree NOC Based MPSOC on Mesh-of-Tree FPGA Devices (Nov. 21, 2011)
  We developed a a Network on Chip (NoC) with Mesh of Trees topology that has been proposed in literature, this particular topology is implemented into 2 different FPGA devices the Xilinx Virtex4 and the AboundLogic Raptor 750. The Raptor FPGA has a mesh of trees as routing interconnect structure, while the Virtex 4 routing is based on a Manhattan Structure. Our paper examines the potential benefits of the correspondence in topology of logical and physical interconnect. Results shows an important boost in performance level but less gain in resources usage.
  
  
• A brief primer on embedded SoC packaging options (Nov. 21, 2011)
  This article addresses the basics of packaging such as types of packages and their advantages and disadvantages, future trends, and factors to be considered while choosing a package.
  
  
• e-MMC vs. NAND with built-in ECC (Nov. 18, 2011)
  This article will explore the attributes of and differences between e-MMC and NAND with built-in ECC – as well as go into detail about the applications that are best suited for each.
  
  
• SerDes chip enables integration of multiple video streams (Nov. 18, 2011)
  This article describes a parking assistance system using four camera sensors, connected to an FPGA baseboard through the serializer/deserializer (SerDes) interface chip. Specifically, the FPD-Link product family is designed for serial interfaces of embedded displays and camera sensor systems, and also has industrial applications.
  
  
• Building a high-performance camera for wood inspection (Nov. 09, 2011)
  This high-performance wood-inspection system is based on a VITA1300 image sensor and an XEM5010 FPGA integration module
  
  
• Stellamar's all-digital, fully-synthesizable, analog-to-digital converters for Microsemi FPGAs (Nov. 09, 2011)
  This all-digital ADC requires no analog block design; only a few passive components are necessary
  
  
• Design and Implementation of an OCP-IP Compliant 64-Node Butterfly Network on Chip on Multi-FPGA (Nov. 07, 2011)
  In this paper, we report the design and multi- FPGA chip implementation of a 64-node butterfly network based on MPSOC. Our Network is placed and routed automatically on the 4 FPGA included in Eve Zebu-UF4 platform.
  
  
• Overcoming 40G/100G SerDes design and implementation challenges (Nov. 02, 2011)
  Increasingly higher-bandwidth requirements continue to drive development and demand for 40G and 100G systems. To implement these link speeds, SerDes devices must meet tighter performance specifications, with extremely high speeds running at extremely low bit-error-rates (BER).
  
  
• Distributed Video Coding: Adaptive Video Splitter (Oct. 31, 2011)
  In this paper, an adaptive video splitter (AVS) design and implementation details, which can also improve RD performance with significantly higher motion video sequences, are presented. This paper is backed up with experience of developing entire DVC codec C model, which is presented in authors other submitted paper.
  
  
• Simple ways to manage different clock frequencies of audio codecs (Oct. 26, 2011)
  Audio processing is essential to many consumer electronic applications such as mobile phones, MP3 players and a host of other products. While size and power consumption are often critical SoC design requirements, the market demands high-quality high fidelity (Hi-Fi) audio capabilities.
  
  
• The basics of low power programming on the Cortex-M0 (Oct. 26, 2011)
  The ARM Cortex-M0 processor has been designed to provide low-power advantages over other processors. In this article I will discuss how some of these features can be used to advantage in programming for this architecture.
  
  
• Big.LITTLE processing with ARM Cortex-A15 & Cortex-A7 (Oct. 25, 2011)
  This white paper presents the rationale and design behind the first big.LITTLE system from ARM based on the high-performance Cortex-A15 processor, the energy efficient Cortex-A7 processor, the coherent CCI-400 interconnect and supporting IP.
  
  
• Implementing high Speed USB functionality with FPGA- and ASIC-based designs (Oct. 19, 2011)
  A wide range of FPGA-based applications exist that can benefit greatly from the addition of a high speed USB interface…