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IP / SOC Products Articles

• Argument for anti-fuse non-volatile memory in 28nm high-K metal gate (Oct. 17, 2011)
  One function that continues to be challenging for on-chip integration is non-volatile memory (NVM) despite its many advantages. At smaller process geometries, especially 28nm HKMG, the challenges to integrating NVM such as flash, pseudo flash, and e-fuse are effectively addressed with an anti-fuse solution.
  
  
• Multi-FPGA NOC Based 64-Core MPSOC: A Hierarchical and Modular Design Methodology (Oct. 10, 2011)
  With the increasing need for real time complex applications, number of processors in the same MPSOC design is becoming a critical parameter to evaluate its performance.
  
  
• Designing a high-definition FPGA-based graphics controller (Oct. 06, 2011)
  Recently, one of our clients came to us looking for a solution to display graphics on LCD monitors. We were informed that any data was to be is generated by a separate device and fed to the graphics controller using an external microcontroller.
  
  
• Debunking the myth of the $100M ASIC (Oct. 04, 2011)
  A false belief that leading-edge chips cost up to $100 million to develop has severely decimated levels of venture capital investment in semiconductors, diminishing innovation in our industry and our economy. The fact is, engineers can create a profitable chip company with less than $2 million of total investment. I know because we have done it.
  
  
• SerDes in High-Reliability, Long Reach Systems (Sep. 19, 2011)
  The paper explores the challenges facing designers implementing systems that are compliant to 10GBASE-KR and CEI11-LR standards. These systems can be 40-50” with multiple connectors and it is desirable to have bit-error-rates (BER) of 10-15 to 10-18 for high-reliability applications, going beyond the specification for these real-world channels.
  
  
• FPGA-based Ethernet switches for real-time applications (Sep. 08, 2011)
  Lattice Semiconductor and Flexibilis have released a Gigabit Ethernet Switch IP core that is scalable, non-blocking, and extensible.
  
  
• USB3.0 application building using low performance 8-bit microcontroller (Sep. 06, 2011)
  This article presents the aspects of building USB3.0 application using low performance 8-bit microcontroller taking an 8051 derivative as an example. First it gives a technical overview of the USB technology and its performance. In the next chapters the example architectures are discusses followed by target applications based on them.
  
  
• Many-Core: Finding the Best Multi-Processing Tile (Aug. 30, 2011)
  A project to create an optimal many-core IP tile tackles the need for massive emulation capability.
  
  
• Hot Chips: the puzzle of many cores (Aug. 25, 2011)
  Papers at Hot Chips 2011 suggest that emphasis is shifting from multicore to manycore.
  
  
• Ultra Low Jitter Wide Band LC PLL (Aug. 22, 2011)
  The accelerating need for ever higher data rates and serial I/O density sets demanding performance requirements for current and next generation SerDes transceivers. The PLL is the key to determining high speed link capabilities, since high quality clocks are required to meet bit error rate (BER) specifications of 10-12 to 10-15. An ultra-low jitter wideband LC PLL has been developed to meet the exacting requirements of today's systems.
  
  
• Distributed Video Coding (DVC): Challenges in Implementation and Practical Usage (Aug. 15, 2011)
  Distributed Video Coding (DVC) is a new coding paradigm for video compression. This paper highlights gaps and challenges in implementation of DVC and its practical usage.
  
  
• SOCs: IP is the new abstraction (Aug. 11, 2011)
  Reusable IP, not system-level language, has become the new level of abstraction.
  
  
• The Importance of True Randomness in Cryptography (Aug. 08, 2011)
  Creating Random Numbers is hard. Especially if all you have available to do it, is digital hardware and deterministic software. Where is the randomness in that? Both are designed to behave predictably, each time, every time. Therefore, hardware and software designers, trying to find unpredictability, have to look outside of their normal operating environment to find it.
  
  
• Interconnect Solutions for 40G/100G Systems (Aug. 01, 2011)
  One of the key challenges with supporting 40G/100G links is that the SerDes must not only support emerging standards such as XLAUI (40G Ethernet) and CAUI (100G Ethernet) but must continue to support current and legacy interfaces such as 1Gbps Ethernet (SGMII) and 10Gbps Ethernet (XAUI). Multi-protocol support is essential to managing the transition to higher data rates while still supporting legacy standards.
  
  
• Design guidelines for embedded real time face detection application (Aug. 01, 2011)
  Much like the human visual system, embedded computer vision systems perform the same visual functions of analyzing and extracting information from video in a wide variety of products.
  
  
• SPVR: An IP core for Real-Time Speaker Verification (Jul. 18, 2011)
  This paper aims at presenting an IP core whose purpose is to perform real-time speaker verification. The IP core can be used as part of a system to check if the speaker is really the one (he or she) who claims to be.
  
  
• ARM Mali-T604 tips mobile graphics, computing, and IP trends (Jul. 07, 2011)
  The ARM Mali graphics core is a departure from years of evolution in the rendering hardware, but points to the future of IP.
  
  
• Application Driven Network on Chip Architecture Exploration & Refinement for a Complex SoC (Jun. 20, 2011)
  This article presents an overview of the design process of an interconnection network, using the technology proposed by Arteris.
  
  
• Moore's Law, the bifurcation of the semiconductor industry and 3-D integration (Jun. 17, 2011)
  With all the gloom and doom facing the semiconductor industry and especially with the "end of Moore's Law" coming up soon as many experts predict, let's look at several facts relating to the unbelievable ride the industry has had for the last 40 years
  
  
• Basics of SoC I/O design: Part 1 - The building blocks (Jun. 16, 2011)
  Integration of analog with digital and increase in on chip features in mixed-signal controllers demand more complex I/O structures as well, but are often the most neglected features of a chip. This two part article will provide the basics for allowing developers to optimize their performance and functionality. Part 1: The I/O building blocks.
  
  
• Basics of SoC I/O design: Part 2 - Hot swap & other implementation issues (Jun. 16, 2011)
  Having dealt in Part 1 with some of the basics of SoC I/O pin assignment, in this second part we will deal with a variety of implementation issues, including hot swap, interrupts, pin assignments and Interfacing with the devices being operated at voltage other than SoC’s core voltage
  
  
• Understanding SD, SDIO and MMC Interface (Jun. 13, 2011)
  This white paper presents very important information for managers, engineers, and system architects who want to broaden his/her knowledge of interfacing with removable data storage devices. There are many different aspects of SD and MMC interfacees and this white paper organize them into a very easy to understand format.
  
  
• Silicon Qualified SuperViC: the only way to safe SoC integration (Jun. 13, 2011)
  System integrators often encounter problems on application boards too late in the design cycle, when bringing together Virtual Components (ViCs of silicon IPs) into a system. Some ViC performances may be degraded at higher levels (SoC and PCB), and thus the final system does not perform as well as expected. In other words, assembling high-performance ViCs together does not guarantee high-performance SoCs or systems when fundamental integration aspects are not addressed or key issues are violated during the integration process.
  
  
• A Case for Custom Power Management ASIC (Jun. 06, 2011)
  As more functionality has been added to the devices, the power requirements have increased. As the power requirement grows, the capacity of the battery has to be increased, increasing the space occupied and its weight. This makes the battery one of the bulkiest component in the handhelds.
  
  
• The Sony PlayStation 3 hack deciphered: what consumer-electronics designers can learn from the failure to protect a billion-dollar product ecosystem (Jun. 06, 2011)
  What threats are designers of consumer-electronic products up against when trying to secure their platforms against attacks? A robust platform security system that begins with a clear set of security objectives is key to meeting the attacker challenge and surviving and recovering from similar onslaughts.
  
  
• Improving today's multimedia products with 3rd-party audio IP solutions (Jun. 06, 2011)
  In the multimedia market, there is insatiable consumer demand to create, transmit and share digital audio and video content. This demand is driving explosive growth in consumer electronic devices requiring audio post-processing software IP to play digital content without comprising audio fidelity or the consumer listening experience.
  
  
• Two methodologies for ASIC conversion (Jun. 02, 2011)
  ASIC vendor eASIC's announcement of a conversion path from their Nextreme structured devices to a fully cell-based ASIC offers an interesting opportunity to reflect on conversion methodologies. Comparing it to a recent discussion of the KaiSemi conversion flow, which takes a design from an FPGA to a cell-based ASIC, further illuminates some of the important choices that come up in reworking an existing design. The two approaches are conceptually similar, but practically quite different.
  
  
• Advanced Power Management in Embedded Memory Subsystems (May. 16, 2011)
  This paper addresses minimizing low-power design complexity with power, performance and density optimized IP. It covers the power problem, and the complexity of designing with multiple power domains in SoC designs that contain embedded memory. The paper includes the trade-offs and benefits of various power management features as well as the implementation of the design for superior testability by providing optimal test resource partitioning.
  
  
• STAC: Advanced inter-die communication Technology (May. 16, 2011)
  This paper outlines recent a new architecture for implementing a communication channel between two highly-integrated dice. It shows how the on-chip interconnect can be extended to bridge between chips while retaining high bandwidth and low latency. In addition, the technique allows other signals to be integrated into this communication channel without side band signals in a low pin-count and low power architecture. This arrangement provides a universal link which allows the cooperation of multiple chips within a package which may have been designed independently.
  
  
• NoC Interconnect Improves SoC Economics (May. 09, 2011)
  The concise research paper, "NoC Interconnect Improves SoC Economics: Initial Investment is Low Compared to SoC Performance and Cost Benefits," by Objective Analysis Semiconductor Market Research, provides quantitative data from user experiences comparing the costs and benefits of implementing network on chip SoC interconnects versus traditional bus and crossbar interconnects.