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IP / SOC Products Articles

• Performance Measurements of Synchronization Mechanisms on 16PE NOC Based Multi-Core with Dedicated Synchronization and Data NOC (Sep. 08, 2011)
  Multi-core are emerging as solutions for high performance embedded systems. Although important work have been achieved in the design and implementation of such systems the issue of synchronization mechanisms have not yet been properly evaluated for these targets. We present in this work synchronization performance evaluation results on a 16PE NOC based multi-core which we designed and implemented on a single FPGA chip. All reported results come from actual execution and show hybrid synchronization mechanisms best fit the multi-core configurations.
  
  
• Performance Evaluation of Inter-Processor Communication Mechanisms on the Multi-Core Processors using a Reconfigurable Device (Aug. 04, 2011)
  . In this paper, we propose several inter-processor communication mechanisms for two multi-core processors on an FPGA as the primitive operations for the system tasks and evaluate them. We adopted NIOS II processor as the embedded processors and the TOPPERS/ FMP kernel as the operating system for multi-core processor.
  
  
• Power Optimization in Image Superscalar IP (May. 23, 2011)
  In this paper we have present an optimize power aware architecture named as “Cluster Memory Architecture”. This Architecture is implemented in Design and Development of 60 fps Super Scalar IP which can convert 60 VGA Frame to Full HD Frame per second. This architecture ensures similar or reduction of power consumed for same size Single Port SRAM Memory and similar performance as Dual Port RAM. This architecture also facilitates for Switching Off the un-used segment of the memory
  
  
• COMSIS 802.11n: an IP to Reuse - a flexible platform for Design (May. 09, 2011)
  In this paper, we present 802.11n Comsis IP and the Comsis WiFi evaluation board. First, we summarize 802.11n recommendation features explaining why the MIMO technology performs so well.
  
  
• Implementing Different Power Features in an IP (Apr. 04, 2011)
  One of the challenges for present SoC designers is to ensure that their SoCs consume least power. Since almost all SoCs use a set of IPs, it’s important for the IP providers to give different power reduction options in their IPs, enabling the SoC designers to design a power optimized chip. This paper primarily focuses towards IP design and verification engineers and lists some useful power reduction features that can be implemented in an IP.
  
  
• Understanding and selecting higher performance NAND architectures (Dec. 10, 2010)
  This article is intended to help system and memory subsystem designers understand the differences and benefits of some of the newer NAND architectures.
  
  
• Hyper pipelining of multicores and SoC interconnects (Nov. 04, 2010)
  In this paper, a method is discussed: How the functionality of a core can be multiplied by just adding registers to the core. Not only does this result in less area usage compared to its individual instantiations, but it can also have a substantial beneficial impact on the system performance as a whole. This method is called “hyper pipelining”.
  
  
• SATA Connectivity solutions for Xilinx FPGAs (Oct. 18, 2010)
  This Whitepaper gives an overview over the Serial ATA (SATA) protocol and the implications when integrating SATA into an FPGA-based programmable system. Besides details of the different protocol layers, we will discuss the hardware and software components for building a complete, reliable, high-performance SATA solution by utilizing a design platform from Missing Link Electronics (MLE).
  
  
• How to Choose Great IP (Oct. 04, 2010)
  Many chip designers use IP to improve their productivity, but unfortunately not all IP is created equal. Ed Bard, senior director of marketing, IP, and Ralph Morgan, vice president of engineering, IP, both of Synopsys, suggest that to separate the good from the bad, design teams must exercise proper due diligence when selecting IP.
  
  
• Avoiding design errors in 1394-based external storage systems (Sep. 28, 2010)
  While IEEE 1394/Firewire is a popular and proven standard familiar to many system designers, there is still the potential to make design errors that can compromise performance. Here are some tips for avoiding such problems
  
  
• The basics of SerDes (serializers/deserializers) for interfacing (Sep. 17, 2010)
  SerDes (serializers/deserializers) are devices that can take wide bit-width, single-ended signal buses and compress them to a few, typically one, differential signal that switches at a much higher frequency rate than the wide single-ended data bus.
  
  
• Conquering the memory bottleneck (Sep. 14, 2010)
  The evolution of high-bandwidth, consumer system on chip (SoC) devices is driving new design requirements as developers look for innovative ways to conquer bandwidth and efficiency issues on-chip. Today’s most popular home entertainment and mobile devices, such as smart phones, pad computers, high-definition TVs and personal media players, require an ever increasing number of processors that are dependent on sharing the same DRAM pipe. This has generated a substantial efficiency bottleneck for SoC designers and system architects.
  
  
• Extreme Design: Realizing a single-chip CMOS 56 Gs/s ADC for 100 Gbps Ethernet (Aug. 26, 2010)
  A 100-Gbps coherent receiver needs four 56-Gs/s analog/digital converters (ADCs) and a tera-OPS DSP which dissipate only tens of watts. This paper discusses the forces pushing towards a single-chip CMOS solution, and the challenges in realizing this.
  
  
• Harness speed, performance, signal integrity, and low current advantages of 65nm QDR family SRAMs (Aug. 24, 2010)
  This article describes in detail the advantages of the 65nm technology QDR family devices over their 90nm technology equivalent and provides guidelines for simplifying the migration from 90nm to 65nm technology.
  
  
• Dual core architectures in automotive SoCs (Aug. 24, 2010)
  Automotive SoCs have traditionally been single core, since not much computational work or high end applications were targeted on them. Automotives were simpler, so were the applications and so were the SoCs. As more and more electronics made room in the automotives, the complexity of the SoCs kept on increasing. Now the focus is to have most of the automotive under electronic control.
  
  
• MIPI M-PHY takes center stage (Jul. 12, 2010)
  The curtain is up and the M-PHY specification is taking center stage, positioned to handle the many different roles required for a faster, more reliable, physical interface layer (PHY Layer) on mobile devices.
  
  
• SuperSpeed USB (USB 3.0): More than just a speed increase (Jul. 05, 2010)
  SuperSpeed USB (USB 3.0) has been getting a lot of attention now as products become available in the market. The most obvious benefit is the more than 10 times increase in speed over USB 2.0 high-speed; 480 Mbps to 5 Gbps – but there are several others. This article looks at what is new and better with SuperSpeed USB protocols and power management versus USB 2.0.
  
  
• Multiplexed Energy Metering AFEs Ease ASIC Integration and Provide Significant Cost Reduction (Jun. 21, 2010)
  Today’s energy metering standards demand higher accuracy and lower power consumption which, in turn, challenges system designers to deliver more competitive AFEs. This article reviews those challenges and presents a solution based on a multiplexed channel architecture that delivers ultra-high resolution, along with very low-power consumption and silicon area.
  
  
• Advancing Network Packet Management and Security Using Silicon Based Subsystem IP Solutions (Jun. 17, 2010)
  The growth of the Internet continues to drive the need for faster network packet management and improved network security. One way to improve both performance and security effectiveness is to reduce the physical number of hardware and software components that make up OSI Layer 2-4 solutions in the network using an integrated silicon based “subsystem” approach.
  
  
• Low Power Verification of Connectivity IP cores - a USB HS-OTG Case Study (Jun. 14, 2010)
  This paper focuses on the verification challenges and the methodology used to verify a low power design that embeds a combination of techniques to save power.
  
  
• Building Cost Effective and Robust SoC-based Network Appliances (Jun. 01, 2010)
  Krishnan Venkataraman is VP of Engineering at MosChip Semiconductor Technology Ltd.
  
  
• Breaking the 2 Giga Access Barrier: Overcoming Limited I/O Pin Counts (May. 31, 2010)
  Cisco’s Visual Networking Index forecasts that the Internet growth will quadruple by 2013. Projected Internet traffic will approach 1 Zettabyte (1 trillion Gigabytes) per year. To support this amazing trend, the next generations of networking equipment must offer new levels of packet forwarding rates and bandwidth density. This in turn will necessitate new generations of packet processors and the memory subsystems to support these increased demands. MoSys is stepping up to this challenge by introducing a new class of device to accelerate access to packet forwarding information, statistics calculations and packet storage.
  
  
• Selecting the right Nonvolatile Memory IP: Applications and Alternatives (May. 25, 2010)
  With the myriad NVM technologies available, the challenge for system engineers is to do a thorough and critical assessment of the real needs their designs and second, to to understand the benefits and trade-offs for each.
  
  
• The 'off-the-shelf' IPs for today's SoCs (May. 24, 2010)
  Today SoC designs are highly complex with many functionalities. Do these functionalities need to be developed entirely in-house? Rather not! Here is some advice on when you should choose third party IP vendor instead of developing standard component in-house.
  
  
• A Novel Mesh Architecture for On-Chip Networks (May. 06, 2010)
  2D Mesh is a very popular topology in Network on Chip due to its facilitated implementation, simplicity of the XY routing strategy and the network scalability. On the other hand, 2D Mesh has some disadvantages such as long network diameter as well as energy inefficiency because of the extra hops. Due to this, in this work, we propose a novel NoC topology called Diametrical 2D Mesh and related shortest path routing algorithm called Extended XY.
  
  
• Integrating analog video interface IP into SoCs delivers superb image quality (Part II) (May. 03, 2010)
  This two-part series discusses the implementation of analog video interfaces that can be embedded into complex SoCs. Part two provides a detailed review of the analog video interface receiver, which is based on a video analog front-end. Key characteristics are covered, highlighting the special features embedded into the IP that allow it to recreate a high-quality image on the destination side.
  
  
• Choosing the best Standard Cell Library without falling into the traps of traditional benchmarking methods (Apr. 26, 2010)
  Assessing the comparative performances of several Standard Cell Libraries in a reliable way is a tricky project as it deals with statistical issues. The objective of this paper is dual. The first objective is to demonstrate that the « cell-by-cell » approach to compare libraries is inconsistent with actual performances results obtained after P&R of libraries on a logic circuit. The second objective is to present benchmarks and methods to compare efficiently and reliably different libraries with different architectures (e.g. CCSL versus RCSL).
  
  
• Maximizing the value of your IP (Apr. 23, 2010)
  There is no doubt that leveraging IP for reuse is here to stay. The economic and time-to-market advantages are too enormous to forego. However, there are serious challenges to overcome given the high cost of verification and the risk of collateral design damage consequential to RTL modification.
  
  
• Developing a test plan to make your design HDMI 1.4 compliant (Apr. 15, 2010)
  How to use the Agilent E4887A TMDS signal generator to test the quality of HDMI system cables and connectors, and other components for compatibility with Version 1.4 of the spec.
  
  
• PP: An Application-Specific Processor for Manycore Architectures (Apr. 12, 2010)
  The Protocol Processor (PP) is an application-specific processor employed in several products at Lantiq. In this paper we discuss the limitations of simple application-specific processors within manycore architectures and we report on our work on the PP to eliminate or mitigate these limitations.