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IP / SOC Products Articles

• Verification of USB 3.0 Device IP Core in Multi-Layer SystemC Verification Environment (Mar. 17, 2011)
  The paper describes the methodology used for functional verification of the USB 3.0 device controller core. The core model has been developed at two different levels of abstraction: RTL model for synthesis and SystemC TLM model for high speed simulation, early software development and early test-bench creation.
  
  
• Hardware Solutions to the Challenges of Multimedia IP Functional Verification (Feb. 14, 2011)
  This paper discusses the functional verification of IP cores and problems which arise during their implemenation in today’s advanced applications. First, the usual approach to functional verification is presented together with its common difficulties. The next part features an example of hardware verification environment which was used for verification of the Evatronix JPEG 2000 encoder multimedia IP core in order to illustrate this paper’s thesis. After a short description of the JPEG 2000 image compression algorithm, the structure of the environment is presented. Then the manner of test cases preparation is described as well as criteria used to determine whether a particular test is passed or failed. Finally, numerical results of hardware verification experiment are presented with some comments which conclude the paper.
  
  
• Low Cost Solution for Microcontroller In-system Power-up Behaviour Evaluation (Dec. 06, 2010)
  This paper discusses about a low cost, portable, reusable platform established to ease the in-system power-up behaviour evaluation of MCU. This flexible platform is able to generate ramp-up signals at different speeds, starting at different initial voltages, which reduce the first silicon evaluation cost and time significantly. The focus would be mainly on 2 aspects; power-up sequence evaluation, and the low cost test setup with thought of reuse.
  
  
• Choosing the best Standard Cell Library without falling into the traps of traditional benchmarking methods (Apr. 26, 2010)
  Assessing the comparative performances of several Standard Cell Libraries in a reliable way is a tricky project as it deals with statistical issues. The objective of this paper is dual. The first objective is to demonstrate that the « cell-by-cell » approach to compare libraries is inconsistent with actual performances results obtained after P&R of libraries on a logic circuit. The second objective is to present benchmarks and methods to compare efficiently and reliably different libraries with different architectures (e.g. CCSL versus RCSL).
  
  
• Maximizing the value of your IP (Apr. 23, 2010)
  There is no doubt that leveraging IP for reuse is here to stay. The economic and time-to-market advantages are too enormous to forego. However, there are serious challenges to overcome given the high cost of verification and the risk of collateral design damage consequential to RTL modification.
  
  
• Developing a test plan to make your design HDMI 1.4 compliant (Apr. 15, 2010)
  How to use the Agilent E4887A TMDS signal generator to test the quality of HDMI system cables and connectors, and other components for compatibility with Version 1.4 of the spec.
  
  
• PP: An Application-Specific Processor for Manycore Architectures (Apr. 12, 2010)
  The Protocol Processor (PP) is an application-specific processor employed in several products at Lantiq. In this paper we discuss the limitations of simple application-specific processors within manycore architectures and we report on our work on the PP to eliminate or mitigate these limitations.
  
  
• Integrating analog video interface IP into SoCs delivers superb image quality (Part I) (Apr. 07, 2010)
  This two-part series discusses implementation of analog video interfaces that can be embedded into complex SoCs. Part one focuses on the transmitter part of the analog video interface, which is essentially a digital-to-analog converter with video performance, and discusses the characteristics of the source and of the transmission medium.
  
  
• DDR3 memory interface controller IP speeds data processing applications (Apr. 06, 2010)
  In order to fully capitalize on the benefits of DDR3 memories, it is important to have an efficient and easy to use DDR3 memory interface controller. A video processing application provides a good example of the key requirements of a DDR3 memory system and the features needed from a DDR3 Interface in similar stream-oriented data processing systems.
  
  
• Design of an image-processing device for cost-sensitive, high-volume applications using a novel dynamically reconfigurable technology (Apr. 05, 2010)
  Many devices could benefit from programmability, but high-volume, cost-sensitive applications often force device manufacturers to use hard-wired RTL design techniques for reasons of end device cost. This results in the need for multiple silicon implementations to support different device variants, and means that device manufacturers are slow to respond to changing market requirements owing to the time taken to redesign, verify, manufacture and test a new device variant. Though programmability is highly desirable, the complete flexibility of function provided by a CPU or DSP-based solution is rarely necessary. This paper illustrates a design approach that uses a novel dynamically reconfigurable logic (DRL) technology to produce a device that is just reconfigurable enough to meet the flexibility requirements of the manufacturer whilst not imposing a significant size or power overhead compared to traditional RTL-based design techniques.
  
  
• A Flexible, Field-programmable ROM Replacement (Mar. 15, 2010)
  For large amounts of on-chip code and data, mask read-only memory (ROM) provides an inexpensive and easily programmed storage mechanism. However, the inability to configure ROM after wafer processing means that information stored in the ROM cannot be changed in the field. Antifuse one-time programmable (OTP) provides a flexible, field-programmable alternative to ROM. An antifuse-based bit cell uses controlled, irreversible thin (gate) oxide breakdown to program a bit.
  
  
• Initial Investigations into UML Based Architectural Reference Patterns for Set-Top Boxes (Mar. 08, 2010)
  This paper analyses a leading-edge Set-top Box (STB) design for architecture reference patterns. Specifically, the following contributions are made: (i) identifying and documenting (in UML) STB architectural reference patterns, and (ii) providing empirical (quantitative) analysis of pattern use.
  
  
• Selecting an embedded MCU: How to avoid evaluation trap? (Mar. 08, 2010)
  The main goal of this article is to focus on the difficulties encountered by SoC integrators when selecting an embedded microcontroller (MCU). Indeed, the selection is based on MCU performances, but the comparison can be difficult and compromised when considering all the parameters influencing these performances.
  
  
• Embedded Symmetric MultiProcessing system on a SoC with 1.6GHz PowerPC IP in 45nm (Mar. 01, 2010)
  Because the dimensions of lithography are now closer to the fundamental physical limits, scaling is more and more difficult and thus multi-core processor solutions are just starting to be more popular in the embedded area. This paper describes in details the features that allow SoCs to be built with up to eight 1.6 GHz PowerPC CPU cores in an embedded system supporting Symmetric Multiprocessing (SMP) architecture. The balancing between CPU execution speed, memory bandwidth and latency, and coherency overhead has been the objective of the design of the PLB6 and the L2 Cache IP's, to reduce as much as possible the drop-off in performance-per-core inherent in an SMP approach.
  
  
• Evolving to a Total IP Solutions to Accelerate SoC Design (Mar. 01, 2010)
  With validation and software development becoming a prominent bottleneck in a project, progressive IP providers such as Arasan Chip Systems offer a Total IP Solution to address these demands. In this paper we explore the evolving SoC design model and propose a Total IP Solution approach as the next logical step for IP product companies.
  
  
• My FPGA's not working: Problems with the IP (Feb. 18, 2010)
  In my previous post I waffled on about the challenge of RTL mismatches in an FPGA methodology. This week we'll look at how using third-party IP can also introduce some nasty little issues
  
  
• Re-Configurable Platform for Design, Verification and Implementation of SoCs (Design and Verification without Constraints) (Feb. 11, 2010)
  We propose a new methodology flow which will allow the visual definition of a complex SoC through instantiation of parametric IP such as processors, SDRAM controllers, DMA engines, on-chip buses, peripherals, switch matrices and coherency directories, coprocessors, etc.
  
  
• Module Threading Technique to Improve DRAM Power and Performance (Feb. 01, 2010)
  This paper provides details of all DRAM timing constraints which have heavy impact on memory system performance and introduces module threading technique to overcome these limitations. It also provides detailed theoretical analysis on how module threading can offer finer granularity, higher bandwidth and importantly lower power consumption. It also provides board level analysis where 25% power was saved and a higher performance achieved by adopting module threading technique.
  
  
• Using SerDes in Fourth Generation Wireless Infrastructure (Jan. 26, 2010)
  As the network equipment infrastructure is built up for 4G there will be an demand for high serial data rates between the main control radio equipment and that in distributed base stations. Here is how to meet the high serial data rate by only ugrading the Serdes through the use of a discrete solution
  
  
• A nuts and bolts engineering approach to using open source IP (Jan. 26, 2010)
  Mindtree's Girish Managoli provides some practical advice about preparing the documentation on products based on open source IP, before handing it over to management and the legal department.
  
  
• Viewpoint: Need to move beyond the network-on-chip (Jan. 05, 2010)
  With today's design starts using 65nm design rules or smaller, the number of cores in an SoC can exceed 100. Connecting 50 or 100 cores breeds challenges that SoC design teams did not have to previously face.
  
  
• A 66-mW 3.4Gbps Transmitter PHY for HDMI Applications in 2.5V 40-nm CMOS (Jan. 04, 2010)
  This paper presents a low-power Synopsys® DesignWare® High Definition Multimedia Interface Transmitter (HDMI TX) PHY in a 2.5V 40-nm CMOS process. It employs a number of features for IP portability and ultra-low power consumption. The DesignWare HDMI TX IP includes a half-rate serializer, a low-power PLL and clocking scheme in addition to a novel TX architecture. The architecture is portable into both 2.5V and 1.8V process nodes, and makes use of a “supply-less” termination scheme that eliminates the need for a 3.3V supply.
  
  
• Designing Serial ATA IP into your embedded storage device design (Dec. 15, 2009)
  Due to this demand, the SATA interface is increasingly becoming available as third party intellectual property (IP) to help speed development time and lower costs. The quality, completeness and interoperability of this IP become the key considerations to the SoC integrator. This article describes the SATA complete IP solution for both host and device applications.
  
  
• The SoC in 2020: Advances to redefine how we live (Dec. 07, 2009)
  In this fourth installment of TI's 2020 Vision series, Senior Fellow Bill Witowsky (retired) explains why the inherent functionality of future high-performance SoCs will be defined by software in order to facilitate the repurposing required to offset their development costs.
  
  
• PRODUCT HOW-TO: Increase embedded processor efficiency through the use of distributed processing blocks (Nov. 30, 2009)
  How to incorporate distributed multiprocessing in an embedded design using the Cypress PSoC 3/PSoC 5, which incorporate a main 8051 or Cortex M3 core and many Universal Digital Blocks (UDBs) serving as an array of mini-processors.
  
  
• Using IEEE-1588 transparent clocks to improve system time synchronization accuracy (Nov. 30, 2009)
  When deploying IEEE-1588 for system time synchronization in a network design, it is necessary to consider the timing accuracy you require, and how well the slave you want to use performs. Here are the basics on how to achieve this goal.
  
  
• Using OCP and Coherence Extensions to Support System-Level Cache Coherence (Nov. 12, 2009)
  In this paper, the concept of OCP coherence extensions is proposed. Moreover, a possible OCP-based coherence design utilizing the proposed OCP coherence extensions to support system-level cache coherence is also demonstrated.
  
  
• Multi-core, multi-IP reduce development time for infotainment apps (Nov. 09, 2009)
  With its new SH7786, Renesas has expanded its commitment to modular multimedia processors and complete multimedia system solutions for the automotive industry. This evolutionary approach, based on current architectures, ensures low-risk system integration.
  
  
• Incorporating Quality into Reusable Interface IP (Nov. 09, 2009)
  Today’s complex silicon-on-chip (SoC) designs contain multiple instances of silicon intellectual property including CPUs, DSPs, and large numbers of interface IP—SD, SDIO, USB, and MIPI—to store and route video, audio, and data within these designs. On some large SoCs, as much as 85 percent of silicon real estate is made up of third party IP.
  
  
• Graphics processing: When DIY just doesn't make sense (Nov. 05, 2009)
  High-end displays are gaining ground, and designers are urged to develop more advanced graphics processing. To lower the cost of ownership, ARM suggests licensing of an integrated GPU solution that includes software and hardware.