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IP / SOC Products Articles

• A multi-purpose Digital Controlled Potentiometer IP-Core for nano-scale Integration (Nov. 23, 2009)
  This paper presents a highly portable and configurable Digital Controlled Potentiometer (DCP) IP core which comes along with a novel, mainly automated IP integration and characterization process with excellent porting capabilities. The DCP-IP core is optimized to be used as a DAC and an SAR-ADC in a wide specification range.
  
  
• What if the IP you are looking for does not exist? (Oct. 26, 2009)
  Designing a modern SoC is in great part a job of selecting and integrating existing IP cores from third parties. This represents a tremendous acceleration and cost reduction in the design process when compared to maintaining a multidisciplinary design team in house.
  
  
• Integrated Power Management, Leakage Control and Process Compensation Technology for Advanced Processes (Mar. 16, 2009)
  This paper describes a unique suite of power management, leakage control and process compensation technology geared towards reducing power while optimizing performance. This integrated solution, including advanced algorithms, innovative circuits, unique devices and structures, software and manufacturing optimization methods, will be discussed. Silicon performance results will be reported.
  
  
• Pipeline vs. Sigma Delta ADC for Communications Applications (Mar. 16, 2009)
  The Analog-to-Digital Converter (ADC) is a key component in digital communications receive channels, and the correct choice of ADC is critical for optimizing system design. In this article, we discuss what design factors drive the selection of the ADC, how to specify the ADC and when to choose between a Pipeline ADC and a Sigma-Delta (Σ/Δ) ADC.
  
  
• Debug and testability features for multi-protocol 10G Serdes (Mar. 09, 2009)
  The paper describes the design-for-test (DFT) features of a 10.3125Gb/s Serdes and other such high datarate IP as XAUI, PCIe, and others. It is shown that extensive testability can be implemented in a high data-rate Serdes. The paper describes the bench-test and characterization features, as well as wafer and production test considerations.
  
  
• The VP8 video codec: High compression + low complexity (Mar. 02, 2009)
  On2 VP8 achieves high compression with a bitstream that is less compute intensive to decode than either its predecessor (VP7) or competing technologies like H.264. Here's how it works.
  
  
• PCI Express Gen 3 Simplified (Feb. 27, 2009)
  In early 2008, the PCI-SIG announced the establishment of a workgroup chartered with the development of the next generation of PCIe " the PCI Express Base Specification 3.0, or PCIe Gen 3. The Gen 3 specification is yet another step forward in enhancing the usefulness of the PCIe protocol by doubling the effective bandwidth and adding protocol enhancements to increase end-system performance.
  
  
• Analysis: BDTI benchmarks the CEVA-TeakLite-III (Feb. 26, 2009)
  BDTI has released BDTI DSP Kernel Benchmarks results for the CEVA-TeakLite-III core from CEVA. The CEVA-TeakLite-III competes with a range of general-purpose DSP and CPU cores from vendors such as VeriSilicon, ARM, and MIPS, and also with application-specific audio solutions, such as Tensilica's 330HiFi audio core and ARC's Sound Subsystems cores.
  
  
• How to pick a RapidIO switch (Feb. 23, 2009)
  Designers have many different options for implementing a RapidIO interconnect. This article outlines the decision factors that designers should consider, organized by project development phases: system design, implementation, system verification, and system evolution. A last section discusses support services, which impact all stages of project development.
  
  
• DDR SDRAM Controller IP Designed for Reuse (Feb. 19, 2009)
  This paper deals with reusability issues in the development of a double data rate (DDR) SDRAM controller module for FPGA-based systems. With our approach, it is possible to generate a highly reconfigurable DDR controller that minimizes the recoding effort for hardware development.
  
  
• Dynamic instruction set load-in method for Java SoC (Feb. 12, 2009)
  There are varieties of embedded systems in the world, it’s a big challenge to optimized the instruction sets of SoCs according to different systems’ working environments. The idea of dynamic instruction set is a good method to achieve the embedded system’s re-configurability. This paper presents a convenient method for a Java processor to work with dynamic instruction set in the form of FPGA or ASIC.
  
  
• Migrating from SPI 4.2 to SPI 5 IP Core - Architectural Changes and Re-usability (Feb. 09, 2009)
  This article discusses the architectural changes and IP re-usability scope for modifying an existing SPI 4.2 Transmitter and Receiver IP Core. SPI 4.2 and SPI 5 have a great deal of functional similarity which makes this IP migration smoother. The paper considers an existing SPI 4.2 IP core and examines the architectural changes and re-usability of the sub-modules. The addition of a few modules, which are a part of SPI 5 protocol, is also highlighted.
  
  
• A Platform for Performance Validation of Memory Controllers (Feb. 02, 2009)
  With growing gap between processor and memory speeds, the memory bandwidth has become performance bottleneck for media applications. The memory controller designs are getting optimized to reduce the latencies added by them. It is necessary to prove the performance of memory controller on prototypes. It has been observed that the performance calculated in simulations is very difficult to achieve on prototype board. This is mainly because of subsystem limitations.
  
  
• SAS--SATA: What You Need to Know for 6 Gb/s and Beyond (Jan. 26, 2009)
  New SAS-2 and SATA Gen-3 system protocols enable 6 Gb/s link speeds between storage units, disk drives, optical and tape drives, and protocol host bus adapters. Here are the challenges to maintaining signal integrity at 6 Gb/s and how improper test setups degrade signals during development and test.
  
  
• Identifying IP cores -- to protect your investment (Jan. 26, 2009)
  In this paper, Semiconductor Insights shows some noble ways of identifying IP cores from any SoC products to protect the interest of IP core providers. Techniques developed by Semiconductor Insights to identify IP core blocks include methods such as circuit extraction using advanced delayering techniques, layout comparisons, automatic recognition and extraction of standard cells and blocks of designs, netlist generation from the extracted circuits, use of circuit library to identify IP blocks, use of structural data mining algorithm for netlist comparison, and device and system level testing to identify IPs involving algorithms and system level protocols.
  
  
• Backplane tutorial: RapidIO, PCIe and Ethernet (Jan. 15, 2009)
  RapidIO, PCIe, and Ethernet each offer unique benefits. We explain how each technology works, and examine its strengths and weaknesses. We also show why RapidIO is often the best choice for embedded systems.
  
  
• Inductorless versus Inductor-Based Integrated Switching Regulators: Bill Of Material, Efficiency, Noise, and Reliability Comparisons (Jan. 12, 2009)
  Inductor-based Switching Regulators (SR) have historically represented the preferred architecture for power supplies. Nowadays, for low-power and highly integrated electronic systems, embedded inductor-based SRs show several limitations that can be overcome by the use of inductorless SR architectures. This paper provides a qualitative and quantitative comparison between both types of SR in terms of implementation cost (Bill of Material, and pin count), and performance (efficiency, noise, and reliability).
  
  
• Providing memory system and compiler support for MPSoc designs: Memory Architectures (Part 1) (Jan. 08, 2009)
  System-on-chip (SoC) architectures are being increasingly employed to solve a diverse spectrum of problems in the embedded and mobile systems domain. The resulting increase in the complexity of applications ported into SoC architectures places a tremendous burden on the computational resources required to deliver the required functionality.
  
  
• Providing memory system and compiler support for MPSoc designs: Customization of memory architectures (Part 2) (Jan. 08, 2009)
  To follow on the review and assessment of various memory architectures in Part 1 in this series, we will now survey some research efforts that address the exploration space involving on-chip memories. A number of distinct memory architectures could be devised to exploit different application-specific memory access patterns efficiently.
  
  
• Providing memory system and compiler support for MPSoc designs: Compiler Support (Part 3) (Jan. 08, 2009)
  An optimizing compiler that targets MPSoC environments should tackle a number of critical issues. From the performance viewpoint, perhaps the two most important memory-related tasks to be performed in an MPSoC environment are optimizing parallelism and locality. Other important issues relate to power/energy consumption and memory space.
  
  
• Differentiate your HD multimedia design by customizing the processor core (Jan. 05, 2009)
  The opportunity for product differentiation and the need for programmability now reside in the video pre- and post-processing blocks that improve upon the picture and color fidelity delivered by the digital HD codecs.
  
  
• Use open loop analysis to model power converters with multiple feedback paths (Dec. 22, 2008)
  This article capitalizes on work done with loop stability analysis techniques and explores different ways to apply the them to power converters featuring multiple feedback paths
  
  
• A Generalized Waveform Synthesis Mechanism for Software Radio (Dec. 15, 2008)
  This paper describes a generalized method to achieve Direct Waveform Synthesis (DWS) for different modulation formats both binary and multi-level, in order to include this mechanism in the general functioning of a software based IP-core. Moreover a generalized approach for designing and managing of an IP core, which is based on Linear Algebra and specific programming, is derived from the developed algorithm.
  
  
• Video processing pipeline design (Dec. 04, 2008)
  An experienced designer explains the basics of video processing pipelines. He shows how they resemble classic RISC processor pipelines, and the tradeoffs of Tensilica and Silicon Hive solutions.
  
  
• Video encoding with low-cost FPGAs for multi-channel H.264 surveillance (Dec. 01, 2008)
  Building a high-performance, quad-channel H.264 encoder using low-cost, low-power FPGA architecture.
  
  
• Dealing with clock jitter in embedded DDR2/DDR3 DRAM designs: Part 1 (Nov. 27, 2008)
  This series of three articles explores DDR2/DDR3 clock jitter specifications and provides guidance to embedded systems developers on how to apply them and deal with violations when systems encounter them. Part 1 " Defining Clock Jitter
  
  
• Dealing with clock jitter in embedded DDR2/DDR3 DRAM designs: Part 2 (Nov. 27, 2008)
  This series of three articles explores DDR2/DDR3 clock jitter specifications and provides guidance to embedded systems developers on how to apply them and deal with violations when systems encounter problems. Part 2: DDR2/DDR3 Functionality
  
  
• Dealing with clock jitter in embedded DDR2/DDR3 DRAM designs: Part 3 (Nov. 27, 2008)
  This series of three articles explores DDR2/DDR3 clock jitter specifications and provides guidance to embedded systems developers on how to apply them and how to deal with violations when systems encounter them. Part 3: Clock Jitter and Statistics
  
  
• Build low power video SoCs with programmable multi-core video processor IP (Nov. 24, 2008)
  With power consumption comparable to ASICs, this SoC architecture scales to 1080p and beyond.
  
  
• Built-In DMA Engines Unleash Power of PCI Express Switches (Nov. 13, 2008)
  Direct memory access (DMA) technology has been around for more than 20 years. DMA has been used principally to offload memory accesses (reading and/or writing) from the CPU in order to enable the processor to focus on computational tasks and increase the performance of embedded and other system designs.