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IP / SOC Products Articles

• Enabling Robust and Flexible SOC Designs with AXI to PCIe Bridge Solutions (Sep. 08, 2009)
  A bridge between two standard protocols is an attractive building block for system designers. When designing an application around a standard protocol, a bridge to another protocol enables all of the benefits of that second system with a less-intensive design-process.
  
  
• Placement of different type nodes in a Network-on-chip graph (Aug. 17, 2009)
  In this article we consider effect of different type nodes placement in a network-on-chip to system parameters. We suggest a method of nodes placement that guarantee the potential performance constraints meeting
  
  
• H.264/AVC HDTV Motion Compensation Soft IP (Jun. 04, 2009)
  This paper presents a motion compensation soft IP for H.264/AVC decoding based on the MoCHA architecture. The IP was designed in VHDL and validated by simulation and by prototyping on a Xilinx FPGA platform.
  
  
• Automotive radio receiver harnesses Software Defined Radio (Nov. 10, 2008)
  Auto-qualified, multi-standard digital radio receiver uses software to implement seven standards; signal-processing blocks are functions that can be shared between different standards.
  
  
• Got OCP? The Role of the OCP in Multicore Designs (Nov. 10, 2008)
  A brief exposition on the role of the open core protocol (OCP) in system-on-chip designs and the impact of the newest Version 3.0 on the design of multiprocessor SoCs.
  
  
• An Integrated, Tunable RF Filter: an Enabler for Reconfigurable Front-Ends (Oct. 27, 2008)
  This paper presents the design and performance of a key RF circuit necessary for the realization of a reconfigurable, integrated RF front-end: a tunable frequency, selectable bandwidth, on-chip, “SAW replacement” filter. The on-die tunable filter presented here has a tunable center frequency up to 1 GHz, a selectable bandwidth up to 40 MHz, and an adjacent channel rejection down to 60 dB.
  
  
• Using signal compression to ease migration to a 4G wireless infrastructure (Oct. 20, 2008)
  By employing signal compression, fiber optic bit rates can be reduced to enable the continued use of low cost fiber optic transceivers.
  
  
• Wireless HDMI with low-latency, lossless H.264 video codec (Oct. 20, 2008)
  Wireless HDMI is impractical for single and multiple 1080p uncompressed video signals, but encoding and decoding traditionally creates A/V sync problems and reduces picture quality. How "Super Low Latency" H.264 codec technology overcomes these problems.
  
  
• Real-time driver drowsiness tracking system (Oct. 16, 2008)
  In which the author describes how an FPGA with a flexible, soft-core embedded processor fuels a real-time driver drowsiness tracking system.
  
  
• Low Power Transport Demultiplexer for ATSC and DVB Broadcast Format (Oct. 09, 2008)
  In this paper, we developed low power transport demultiplexer to support MPEG-2 transport streams for ATSC and DVB digital broadcast standards. Novel window based packet identification (PID) and section filtering is presented to provide a cost effective and flexible solution.
  
  
• Audio ADC buffer design secrets: Interfacing to audio ADC sampling circuits (Oct. 06, 2008)
  Effectively interfacing to A/D converter sampling networks can be a challenging undertaking, but undertsanding the fundamentals can help ensure a successful design.
  
  
• In multicore SOC architectures, buses are a last resort (Oct. 02, 2008)
  The one-processor system model that dominated electronic system design since 1971 is now thoroughly obsolete. Today's SOC designers readily accept the idea of using multiple processors in their complex systems to achieve design goals and use the terms "control plane" and "data plane" to describe how these various on-chip processors are used on the chip.
  
  
• How to transform silicon with dynamic reconfiguration (Oct. 02, 2008)
  A microcontroller capable of reconfiguring its resources needs to provide the integration of an ASIC with the configurability of a FPGA...
  
  
• Using micro-benchmarks to evaluate & compare Networks-on-chip MPSoC designs (Sep. 29, 2008)
  Network-on-Chip (NoC) has been recognized as a promising architecture to accommodate tens, hundreds or even thousand of cores. As a result, a number of NoC architectures have been and are being proposed.
  
  
• A FPGA-Based Solution for Enforcing Dependability and Timeliness in CAN (Sep. 11, 2008)
  This paper identifies a fundamental set of shortcomings of the standard CAN protocol and shows how the problem has been tacked in the implementation of the CANELy architecture, a CAN-based infrastructure able of extremely reliable hard real-time communication.
  
  
• An HDTV SoC Based on a Mixed Circuit-Switched / NoC Interconnect Architecture (STBus/VSTNoC) (Sep. 08, 2008)
  This paper presents the interconnect solution adopted for an HDTV SoC developed in HVD division of STM. The SoC is a one-chip satellite HDTV set-top box IC developed in 65nm technology. The interconnect of this HDTV SoC is the first in STM implementing a mixed archi­tecture based on the circuit-switched interconnect named STBus and the new NoC interconnect named VSTNoC.
  
  
• Reinventing JTAG for SoC debugging (Sep. 08, 2008)
  Want a headstart on implementing a new JTAG debug interface into your design? Here's the lowdown on the soon-to-be IEEE 1149.7 standard.
  
  
• LDPC (Low Density Parity Check) - A Better Coding Scheme for Wireless PHY Layers (Sep. 01, 2008)
  802.16e standard known as the Mobile Wimax standard integrates various coding schemes in the Physical layer specification including the most efficient ones, the LDPC. In this article we will present the physical layer baselines, we will then focus on the error correcting codes to finally detail our implementation.
  
  
• Implementation of the AES algorithm on Deeply Pipelined DSP/RISC Processor (Aug. 20, 2008)
  A more efficient implementation of the Advanced Encryption Standard algorithm on a deeply pipelined RISC/DSP engine reduces overall pipeline stalls during its execution.
  
  
• VLSI Based On Two-Dimensional Reconfigurable Array Of Processor Elements And Theirs Implementation For Numerical Algorithms In Real-Time Systems (Aug. 14, 2008)
  This paper is devoted to the development of one type processor arrays, called MiniTera-2 and to the investigations of realization of some real-time algorithms by means of this array.
  
  
• Low Power High Speed All Digital Phase Locked Loops (Aug. 11, 2008)
  In this paper an All Digital phase locked loop is proposed. This PLL can accomplish faster phase lock. Additionally, the functions of frequency comparator and phase detector have been improved and are well synchronized.
  
  
• AMASS Core: Associative Memory Array for Semantic Search (Aug. 07, 2008)
  This paper presents de specification, design and implementation of a high performance search engine core. This core implements a regular Associative Memory Array processing in HW and non-structured data management in SW.
  
  
• Hardware Security Requirements for Embedded Encryption Key Storage (Aug. 04, 2008)
  As the sophistication of global competitors and IP thieves in countries with weak IP protections increases, there exists an increased need for enhanced physical security for sensitive security information such as encryption keys.
  
  
• Antifuse memory IP fuels low-power designs (Aug. 04, 2008)
  Embedded nonvolatile memory is becoming more prevalent in a wide range of chips, particularly for power-sensitive applications.
  
  
• DesignTag: A Thermally Sensed Security Tag to Protect Chip Designs (Jul. 28, 2008)
  This paper introduces a novel "security tag" technology for detecting misuse of semiconductor intellectual property, in the form of a small circuit which is added to the chip design.
  
  
• Low Power Asynchronous Processor With Cordic Co-Processor (Jul. 21, 2008)
  This paper describes the architectural design of RISC based asynchronous microprocessor as an alternative to clocked design.
  
  
• How to select an AES solution (Jul. 16, 2008)
  To achieve higher data throughput designers can use an ASIC or FPGA platform to provide hardware acceleration.
  
  
• FPGA Implementation of DLX Microprocessor With WISHBONE SoC Bus (Jul. 03, 2008)
  DLX is an open source microprocessor, it’s free and it has never been implemented in a commercial ASIC (Application Specific Integrated Circuit) design. The objective of this project is to use the DLX microprocessor implemented with Wishbone bus interface for a SoC (System-on-Chip) design.
  
  
• Reducing system complexity by using a single-supply logic-level shifter (Jul. 03, 2008)
  This article discusses an innovative, multiple-voltage level-shifter topology which demonstrates the dependence of digital circuits on analog fundamentals such as rise/fall times, capacitance, and current/voltage sourcing/sinking
  
  
• Lower voltage next goal for low-power DDR (Jun. 23, 2008)
  Low-power DDR2 (LPDDR2), a next-generation low-power memory technology for mobile and embedded designs that's being defined by companies participating in Jedec standards, offers higher speed, lower- voltage operation, larger capacities and lower pin count than the current generation--and lets nonvolatile memory share the same bus as SDRAM.