D&R Industry Articles | Most Popular | SoC News Alerts |

IP / SOC Products Articles

• The ARM Cortex-A9 Processors (Oct. 08, 2007)
  This whitepaper describes the details of a newly developed processor design within the common ARM Cortex applications profile
  
  
• 1Tb/s 3W Inductive-Coupling Transceiver IP for 3D-Stacked SiP (Oct. 01, 2007)
  The performance gap between computation in a chip and communication between chips is increasing, making inter-chip communication a bottleneck in development of high-performance LSI systems. One approach to realize high-speed interfaces is to shorten the chip-to-chip distance. System in Package (SiP) reduces the chip-to-chip distance significantly by thinning chips and stacking chips on each other in a package, which provides strong motivation to develop high-speed, low-power, and high-density interface between 3-dimensionally (3-D) stacked chips.
  
  
• Demystifying multithreading and multi-core (Sep. 27, 2007)
  Is multithreading better than multi-core? Is multi-core better than multithreading? The fact is that the best vehicle for a given application might have one, the other or both. Or neither. They are independent (but complementary) design decisions. As multithreaded processors and multi-core chips become the norm, architects and designers of digital systems need to understand their respective attributes, advantages and disadvantages.
  
  
• Employ dynamic power reduction in an ASIC (Sep. 20, 2007)
  Increasing battery life without compromising performance and functionality is a prime concern for the handheld market. The form-factor and economics of this market also demand an ever increasing level of integration for these devices.
  
  
• Cost-effective two-dimensional rank-order filters on FPGAs (Sep. 20, 2007)
  Here's how to use FPGAs as co-, pre-, and post-processing hardware acceleration solutions for video and imaging.
  
  
• A Multiprocessor System-on-chip Architecture with Enhanced Compiler Support and Efficient Interconnect (Sep. 10, 2007)
  This paper describes the development of a Multiprocessor System-on-Chip (MPSoC) with a novel interconnect architecture and an enhanced compiler support for programmability.
  
  
• Ultra-low-power DSP design (Aug. 30, 2007)
  Here's how IMEC built a sub-100uW DSP by tuning its algorithm, processor architecture, and memory system, as well as through clock gating. The article presents detailed power results for each optimization.
  
  
• Analysis: ARC's Configurable Video Subsystems (Aug. 29, 2007)
  Adding to its growing portfolio of licensable silicon IP subsystems, ARC has announced five configurable video processing subsystems. The subsystems range from the smallest-size AV 402V to the highest-performance AV 417V, and support multi-standard video encoding and decoding at resolutions ranging from CIF to D1.
  
  
• Smart InterConnects with Smart IP: Joint Enablers for Rapid MultiMedia SoC Development (Aug. 20, 2007)
  For the past decade, the march of Moore’s “Law” has witnessed the phenomenal growth in System on Chip (SoC) gate counts, allowing the implementation of a confluence of sophisticated algorithms at price points feasible for consumer electronics (e.g., HDTVs, DVD recorders, multi-functional mobile phones, etc.). Unfortunately, gate counts over the past decade have grown far faster than IC designers’ productivity. With so much pressure to launch high end consumer products before prices (and margins) erode, generations change, new standard features are added, and additional competition surfaces, every aspect of the design flow requires analysis to see how, if, when, and where time-to-silicon can be shortened.
  
  
• DSP silicon takes many forms (Aug. 20, 2007)
  Here's a guide to the chips use in signal processing: DSPs, MPUS, FPGAs, multiprocessors, massively parallel processors, and more!
  
  
• IP Core for RAID 6 Hardware Acceleration (Aug. 13, 2007)
  As storage requirements and magnetic disk densities increase the need for reliable storage solutions also increase. This IP core, written in Verilog HDL, provides a small and efficient hardware accelerator for performing RAID 6 calculations to provide uninterrupted access to data during both single and double disk failures.
  
  
• Overcoming Wireless USB commercialization challenges (Aug. 09, 2007)
  Today, the face of UWB and Wireless USB technology continues to evolve as it marches toward mass market commercialization. Wireless USB, also known as Certified Wireless USB, is a short-range, high-bandwidth wireless extension to USB that combines the speed and ease-of-use of USB 2.0 with the convenience of wireless technology.
  
  
• Designing with proven implementations of the Inter IC bus (Aug. 09, 2007)
  Because the I2C bus is currently the industry's most widely used serial bus, it behooves a system designer to have a handful of proven implementations on hand. The method you choose - on-chip, bit-banged, or IP-core implementation - depends mostly on the system processor, but nothing is easier than using an approach that is proven and already works. This article includes a working reference for each of the three methods.
  
  
• How video compression works (Aug. 06, 2007)
  BDTI explains how video codecs like MPEG-4 and H.264 work, and how they differ from one another. It also explains the demands codecs make on processors.
  
  
• Analysis: Tensilica's D1 Video Engine (Aug. 02, 2007)
  Tensilica is now offering a high-performance licensable video engine capable of MPEG-4 ASP encoding at D1 resolution. The processor is called the Diamond 388VDO, and it's one of four new dual-core "VDO" video engines from Tensilica.
  
  
• Utilizing UWB in ultra-low power ZigBee wireless sensor nodes (Jul. 30, 2007)
  In this article, we discuss some of the key challenges associated to the design of UWB transmitters. We further present the first reported transmitter complying with the new 802.15.4a standard, which has been implemented in standard 90 nm CMOS technology and shows a record low-power consumption of 1 mW for a net data rate of 0.85 Mbps.
  
  
• Self-timed interconnect enables true IP reuse (Jul. 26, 2007)
  Despite many claims from both third-party IP vendors and from internal IP development groups at chip companies that their IP is reusable from design to design with little or no rework or extra verification, this is simply not the case. Since every IP core "sees" a different environment in each unique design that employs it, chip designers have to expend considerable effort on each design to verify the IP's operation within it.
  
  
• Analysis: CEVA's 32-bit, Dual-MAC TeakLite-III DSP (Jul. 26, 2007)
  The TeakLite-III cores build upon CEVA's earlier TeakLite cores, CEVA-TeakLite and CEVA-TeakLite-II, with which the TeakLite-III is backwards compatible. To meet the precision and throughput demands of its intended applications, which include high-end audio, 3G cellular, VoIP, and portable audio players, the TeakLite-III features support for both 32-bit and 16-bit fixed-point data, and increased MAC throughput relative to the earlier TeakLite cores.
  
  
• Compiler optimization for DSP applications (Jul. 23, 2007)
  Smart selection of compilation options can yield a dramatic code performance improvement. For example, code size can be greatly reduced. This is often a major factor when evaluating the cost of a product, as it has a direct influence on the amount of memory required. This article shows how to improve code size consumption as well as the consumption of other important resources.Smart selection of compilation options can yield a dramatic code performance improvement. For example, code size can be greatly reduced. This is often a major factor when evaluating the cost of a product, as it has a direct influence on the amount of memory required. This article shows how to improve code size consumption as well as the consumption of other important resources.
  
  
• Achieving scalability with switch fabrics in CompactPCI (Jul. 16, 2007)
  The requirements of applications for which embedded systems are being designed vary in complexity, cost and performance widely. Presenting extreme challenges for designers of systems that must support not only a wide range of applications, but a continuously changing set of performance requirements.
  
  
• 3D graphics hardware IP uses OCP bus interface (Jul. 16, 2007)
  Providing scalable high performance low power 3D graphics cores to the embedded space for handheld devices, mobile phones, vehicle navigation systems, amusement game consoles and other embedded graphics applications, DMP has adopted the Open Core Protocol as the standard bus interface for their components.
  
  
• FlexRay - The Hardware View (Jul. 12, 2007)
  FlexRay is an upcoming networking standard being established to raise the data rate, reliability, and safety of the automotive applications of today and tomorrow. Synthesizable FlexRay intellectual property (IP) is now available for those who want to integrate it into a new chip. This paper discusses what the FlexRay IP is and how to implement it; highlighting issues, considerations, and solutions for the system designer.
  
  
• Selection Criteria for Using DDR, GDDR or MobileDDR Memories in System Designs (Jul. 09, 2007)
  This paper will include a short review of the key features of DDR, GDDR and MobileDDR memory architectures, covering power, speed and cost characteristics as well as key functionality differences that can impact overall system architecture. Using real system design experiences each of the main memory architectures will be used to address system design challenges of sustained bandwidth, reliability, access priority, power savings, and interface requirements.
  
  
• Fully Digital Implemented Phase Locked Loop (Jul. 05, 2007)
  This paper shows an approach for a PLL that only uses digital cell libraries. So all integration advantages of pure digital chips are preserved, there is no design effort for a new chip generation and the PLL also can be used in a FPGA. One of the most astonishing feature is the possibility to check the whole functionality with a pure digital simulator. So without an analog simulator like Spice performance values like frequency and jitter can be checked.
  
  
• Data compression tutorial: Part 3 (Jun. 28, 2007)
  Part three of this three-part series explains how JPEG and MPEG compression work.
  
  
• STBus complex interconnect design and verification for a HDTV SoC (Jun. 18, 2007)
  To support High Definition Television (HDTV) application, the System on Chip (SoC) presented in this paper has to support multiple and concurrent internal processes. Most of these operations read data from memory, process them and store the resulting data into memory. Each functional unit of the system is responsible for a specific data processing, but all the data are stored in the same shared external memories.
  
  
• OTP for DCP Key Storage (Jun. 11, 2007)
  Non-volatile storage of encryption keys is an ideal way to securely implement DCP in a variety of electronic devices. However, not all non-volatile memory (NVM) technologies are suited for these applications. This paper will review some available NVM alternatives for DCP-enabled products and describe an innovative logic NVM IP technology that meets the diverse requirements for encryption key storage.
  
  
• Developing a Reusable IP Platform within a System-on-Chip Design Framework targeted towards an Academic R&D Environment (Jun. 07, 2007)
  The ability to design high quality IP and to enable work practices for reuse methodology helps to achieve working SoCs in a timely and efficient manner. This paper describes a methodology for implementing IP reuse practices suited to an academic environmen
  
  
• Video over IP with forward error correction (FEC) (Jun. 04, 2007)
  This low cost Video over IP implementation bridges an MPEG transport stream with an Ethernet-based Internet Protocol network. The design uses real time transport protocol encapsulation, and Pro-MPEG Code of Practice #3 (CoP3) forward error correction
  
  
• How to design an Interlaken to SPI-4.2 bridge (May. 31, 2007)
  The future of networking is about higher bandwidth and lower power. More and more applications, such as video, continue to drive the bandwidth demands placed on networking equipment. At the same time, networking equipment must deliver these higher bandwidths without a dramatic increase in power consumption.