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IP / SOC Products Articles

• Specifying a PLL Part 3: Jitter Budgeting for Synthesis (Feb. 22, 2021)
  This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.
  
  
• Consider ASICs for implementing functional safety in battery-powered home appliances (Feb. 18, 2021)
  This article looks at how functional safety can be applied in home appliances, and examines the economic tipping point of taking an ASIC vs. discrete component route to do so.
  
  
• Enabling AI Vision at the Edge (Feb. 17, 2021)
  Computer vision has made tremendous advances in the last several years due to the proliferation of AI technology. The intersection of big data and massive parallel computing changed the way in which machines are programmed to understand unstructured 2D and 3D data, such as video feeds from cameras.
  
  
• Retiming USB4 over USB-C (Feb. 12, 2021)
  The USB-C connector is the one connector to rule them all. It has wonderful flexibility in its definition and has been widely adopted across different
  
  
• I-fuse: Most Reliable and Fully Testable OTP (Feb. 08, 2021)
  Patented by Attopsemi™, I-fuse™ is a revolutionary non-breaking fuse technology that can be reliably programmed by heat assisted electromigration below a break point. Any cell can be tested as programmable if the initial fuse resistance is low enough (e.g. <400 ohms) to generate enough heat for programming.
  
  
• PUF is a Hardware Solution for the Sunburst Hack (Jan. 26, 2021)
  On December 14, 2020, SolarWinds, which provides network monitoring software to the US government and private businesses, reported one of the largest cyberattacks in history, breaching the data of as many as 18,000 organizations and companies.
  
  
• USB 3.2: A USB Type-C Challenge for SoC Designers (Jan. 26, 2021)
  This white paper outlines applications that benefit from USB 3.2’s increased bandwidth, describes the USB 3.2 specification for USB Type-C™, and explains how the specification affects speed using USB Type-C connectors and cables.
  
  
• It's Time to Look at FD-SOI (Again) (Jan. 25, 2021)
  The emergence of FD-SOI, (fully depleted silicon-on-insulator) and its subsequent maturity over the years, has made it one of the seminal process advancements for low power semiconductor design. Although not as prevalent as the mainstream bulk CMOS process, FD-SOI has provided an important set of benefits to semiconductor product designers.
  
  
• Verifying Dynamic Clock switching in Power-Critical SoCs (Jan. 18, 2021)
  As technology advance, we see complex SoCs emerging in the market with multiple interfaces. These complex SoCs can have multiple clocks driving multiple modules, which may be getting divided further to generate new clocks in the chip and so the complexity increases.
  
  
• Let's make RISC-V connected systems synonymous with security (Jan. 14, 2021)
  If you are designing systems based on a RISC-V architecture, for example to run highly connected applications, you want to include tight, future-proof security. Both for your customers’ experience and your reputation, you want to avoid a breach of security – leaking private data or even changing the functionality. Therefore, security should be part of the fabric of your system.
  
  
• Quantum Tunneling Mechanism in NeoFuse (Jan. 13, 2021)
  NeoFuse is a logic-process compatible non-volatile memory (logic-NVM) using impedance change for data storage in one-time programming (OTP) applications.
  
  
• IO and multiprotocol processing in highly demanding embedded architectures (Jan. 11, 2021)
  Low physical I/O protocols or device management have always been handled by a hardware device, simply because line survey or reaction to a bus change need very short reaction time. It would require a huge amount of processing power in order to be fast enough to comply with the bus management physical and timing requirements.
  
  
• The Four Angles of Examining PUF (Jan. 04, 2021)
  The security of AIoT devices has become increasingly important. In order to ensure that the system’s security functions are working effectively and protecting every node and edge device from information security risks, it is important to generate a unique root of trust in the security system rooted in the chip.
  
  
• The Growing Market for Specialized Artificial Intelligence IP in SoCs (Nov. 26, 2020)
  Over the past decade, designers have developed silicon technologies that run advanced deep learning mathematics fast enough to explore and implement artificial intelligence (AI) applications such as object identification, voice and facial recognition, and more.
  
  
• The Future Of Chip Design (Nov. 23, 2020)
  The future of chip design in a few short years could look entirely different as the semiconductor industry witnesses an advancing trend toward free and flexible, community-supported hardware designs for the long tail of new applications based on custom semiconductor devices
  
  
• Seize the Ethernet TSN Opportunity (Nov. 16, 2020)
  The following sections will take a look at the major Ethernet performance issues and how the extensions address those shortcomings. This will be followed by an overview of the applications of TSN for 5G, industrial automation, automotive invehicle communications and avionics. The paper will conclude with a description of Ethernet TSN solutions offered by Comcores.
  
  
• A MAC-less Neural Inference Processor Supporting Compressed, Variable Precision Weights (Nov. 12, 2020)
  This paper introduces two architectures for the inference of convolutional neural networks (CNNs). Both architectures exploit weight sparsity and compression to reduce computational complexity and bandwidth.
  
  
• Optimizing Floorplan for STA and Timing improvement in VLSI Design Flow (Nov. 09, 2020)
  Static timing analysis is a technique of computing of cell delay and interconnect delay in design (known as path delay) and comparing it against constrain (timing specific) set in SDC file. This paper describes the static timing analysis for a specific design mainly about mem2reg reg2mem and reg2reg setup analysis a kind of detecting and solving the setup violation in design.
  
  
• Avoid HPC Data Traffic Jams with High-Speed Interface IP (Nov. 04, 2020)
  This article examines technology developments that will help accelerate and manage data movement within and between data centers, within servers, and within system-on-chip (SoC) packages.
  
  
• Specifying a PLL Part 2: Jitter Basics (Oct. 22, 2020)
  This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.
  
  
• Understanding Efficiency of Switched Capacitor DC-DC Converters for Battery-Powered Applications (Oct. 12, 2020)
  This application note provides a brief theory on the efficiency in SC DC-DC converters and a comparative efficiency analysis between the two types of switched converter architectures using a typical application case.
  
  
• Creating Domain Specific Processors Using Custom RISC-V ISA Instructions (Sep. 28, 2020)
  When System-on-Chip (SoC) developers include processors in their designs, they face choices in solving their computational challenges. Complex SoCs will usually have a variety of processor cores responsible for varied functions such as running the main application programs, communications, signal processing, security, and managing storage.
  
  
• PUF based Root of Trust PUFrt for High-Security AI Application (Sep. 14, 2020)
  This article will discuss how to strengthen the security of AI systems from the structure of the AI hardware device, to the security requirements, solutions, and etc. To do this, we will use PUFsecurity’s hardware root of trust module, PUFrt, as an example to help readers understand how combining AI application architecture and physical unclonable function (PUF) can benefit hardware security technology.
  
  
• How a voltage glitch attack could cripple your SoC or MCU - and how to securely protect it (Aug. 31, 2020)
  Hackers and criminals have an array of techniques available to them to intrude into, tamper with, disable or destroy electronics products and services. Some of the techniques are invasive, and call for very expensive equipment and deep engineering expertise to analyze and modify nanoscale electronics circuitry.
  
  
• The Answer to Non-Volatile Memory Security Issues at Advanced Nodes: Go Volatile! (Aug. 31, 2020)
  As semiconductor technology nodes continue to push into smaller and smaller geometries, a pattern has emerged: the basic semiconductor components that define the new node – gates, flip-flops, SRAM, etc. – are put in place with relative ease. However, below twenty-eight nm there have been serious challenges to scale Non-Volatile Memory (NVM) in the same way and at the same speed as the standard components.
  
  
• Super Edge Medical SoC (SEMC) (Aug. 27, 2020)
  Post Covid 19, the biggest bet for revival of the industry is on 5G proliferation across the world. It is widely expected that 5G’s Enhanced Mobile broadband (eMMB) with speeds as high as 20X of 4G speed, Ultra reliable and Low Latency Communication ( URLLC) and massive Machine type connectivity (mMTC) will transform the world.
  
  
• Simplifying AC and DC data acquisition signal chains (Aug. 13, 2020)
  This article describes continuous-time sigma-delta (∑-Δ) ADCs that inherently and dramatically solve the sampling problems by simplifying signal chains. They remove the need for antialiasing filters and buffers, and solve signal chain offset errors and drift issues associated with the additional components.
  
  
• DDR IP Hardening - Overview & Advance Tips (Jul. 27, 2020)
  DDR is most critical IP to SoC’s successful operation, because processors in SoC typically spends the majority of its cycles on reading and writing to DDR memory.
  
  
• AI Edge Inference is Totally Different to Data Center (Jul. 23, 2020)
  While inference accelerators started out primarily in the data center, they have quickly moved to edge inference with applications such as autonomous driving and medical imaging. Through this transition, customers are finding out, often the hard way, that the same accelerator that did so well processing images in the data center fails badly in edge inference.
  
  
• At the edge of data processing (Jul. 20, 2020)
  Neural networks’ data processing raises several challenges in terms of performance requirements. Therefore, the cloud was the first location to host this large processing demand, but this is currently evolving .