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IP / SOC Products Articles

• Time-Domain Analog Design: Why and How (Jun. 01, 2020)
  The widespread adoption of scaled CMOS process technologies has made battery-operated consumer devices more powerful, cheaper, and last longer. In the last two decades, CMOS technology scaling has resulted in orders of magnitude reduction in transistor sizes, from 90nm in 2004 to 7nm in 2019 and 3nm in 2024.
  
  
• Accelerating 5G virtual RAN deployment (May. 25, 2020)
  This whitepaper provides an overview of the O-RAN Alliance and the value provided by O-RAN to the carrier industry along with a brief introduction to Comcores, our O-RAN solutions and our role in the O-RAN eco-system.
  
  
• Why Do We Need SERDES? (May. 25, 2020)
  Despite their design and verification complexity, SERDES have become an indispensable part of an SoC block. With SERDES IP blocks now available, it’s helped mitigate any cost, risk, and time-to-market escalation.
  
  
• RoT: The Foundation of Security (May. 18, 2020)
  The goal of this white paper is to provide a primer introduction to RoT and how to choose a right RoT as the trust anchor for a novel hardware based security architecture
  
  
• 5 Tips for Creating a Custom ASIC (May. 05, 2020)
  Custom application-specific ICs (ASICs) can help OEMs significantly cut the cost of overly specified products and streamline bill of materials management. As more and more companies take this route for their designs, here are some key tips to consider when navigating the custom ASIC path.
  
  
• Build Trust in Silicon: A Myth or a Reality? (May. 04, 2020)
  Currently, there is a strong belief among the cyber security experts that hardware security is imperative since it is more efficient, effective, reliable and tamper-resistant than software security. As a matter of fact, providing trusted execution environment (TEE) and embedding a hardware root of trust (HRoT) as the anchor are necessary to provide a firm foundation for electronic systems security.
  
  
• Why Software is Critical for AI Inference Accelerators (Apr. 27, 2020)
  
  
  
• SRAM PUF: A Closer Look at the Most Reliable and Most Secure PUF (Apr. 06, 2020)
  A recent article on the reliability of SRAM PUFs as a security mechanism for connected devices raised points worthy of discussion. Certainly, in today’s ever-more-connected world of the internet of things (IoT) and proliferating 5G networks, hardware-based security is more important than ever. So, if you’re looking for a way to secure a connected device, how do you evaluate the security and reliability of the various options available?
  
  
• NeoPUF, A Reliable and Non-traceable Quantum Tunneling PUF (Mar. 30, 2020)
  PUF stands for “Physically Unclonable Function” and is a physically derived “fingerprint” that serves as a unique identity for semiconductor devices. Their properties depend on the uniqueness and randomness of the physical factors induced during the manufacturing stage of a chip. T
  
  
• Understanding Physical Unclonable Function (PUF) (Mar. 23, 2020)
  A growing number of ASICs, microcontrollers and SoCs embed hardware cryptographic accelerators or software cryptographic libraries. The emergence of the Internet of Things (IoT) will call for an even faster adoption. We now can talk about cryptography pervasion.
  
  
• Shift Power Reduction Methods and Effectiveness for Testability in ASIC (Mar. 16, 2020)
  The purpose of this article is to highlight the different methodologies to reduce power consumption during ASIC manufacture testing. It distinguishes the different architectures & methodologies to optimize power consumption during a test mode of the design with implementation. There are number of techniques to reduce power consumption with different EDA tools available in the industry.
  
  
• Testing Embedded MRAM IP for SoCs (Mar. 02, 2020)
  With momentum building for Spin Transfer Torque MRAM (STT-MRAM) as the leading flavor of embedded MRAM technology, this white paper focuses on unique test challenges for STT-MRAM on-chip memory while considering needs for automotive applications.
  
  
• SRAM PUF is Increasingly Vulnerable (Feb. 19, 2020)
  As semiconductor technology advances, SRAM is becoming outmoded as a reliable PUF security solution.
  
  
• Layout versus Schematic (LVS) Debug (Feb. 10, 2020)
  In ASIC physical implementation, once layout is generated, it must follow all the design rules for successful manufacturing and must match the schematic of the required design. To ensure this in physical verification, Design Rule Check (DRC) is carried out to check whether the layout follows the rules for fault-less manufacturing or not.
  
  
• Choosing the Right IP for Die-to-Die Connectivity (Feb. 03, 2020)
  Higher data rates and more complex functionalities are increasing the SoC size for hyperscale data center, AI, and networking applications.
  
  
• Securing Smart Connected Homes with OTP NVM (Jan. 06, 2020)
  The market for piracy is huge and hackers have become increasingly sophisticated even when security is implemented in hardware. The race between the aggressors and protectors is a battle without end. Smart connected home devices are increasingly storing and processing very sensitive and private user data in addition to attempting to deliver copyright protected content from service providers. Protecting consumer data is vital.
  
  
• Why the Memory Subsystem is Critical in Inferencing Chips (Dec. 23, 2019)
  The number of new inferencing chip companies announced this past year is enough to make your head spin. With so many chips and no lack of any quality benchmarks, the industry often forgets one extremely critical piece: the memory subsystem. The truth is, you can’t have a good inference chip unless you have a good memory subsystem.
  
  
• Enabling security in embedded system using M.2 SSD (Dec. 16, 2019)
  Storage technologies are evolving at a high speed, thanks to new generations of memories such as Nandflash, ReRAM, MRAM and other flavors. That leads in an incredible performance increase in term of bandwidth and latency. By the way, security and data privacy features are still an important feature for critical storage systems.
  
  
• Formal-based methodology cuts digital design IP verification time (Dec. 11, 2019)
  Changing your methods of performing verification can reduce verification time by several weeks.
  
  
• Internal JTAG - A cutting-edge solution for embedded instrument testing in SoC: Part 1 (Dec. 09, 2019)
  This article is divided into two parts. The first part outlines the important features of the IJTAG use model, while the latter part describes a network interface, its architecture, and how it addresses the major challenges of the SoC test.
  
  
• Pyramid Vector Quantization and Bit Level Sparsity in Weights for Efficient Neural Networks Inference (Nov. 28, 2019)
  This paper discusses three basic blocks for the inference of convolutional neural networks (CNNs). Pyramid Vector Quantization (PVQ) is discussed as an effective quantizer for CNNs weights resulting in highly sparse and compressible networks. Properties of PVQ are exploited for the elimination of multipliers during inference while maintaining high performance. The result is then extended to any other quantized weights. The Tiny Yolo v3 CNN is used to compare such basic blocks.
  
  
• Enabling Bluetooth Out-of-Band pairing through NFC (Nov. 18, 2019)
  Many services offered over Bluetooth can expose private data or let a connecting party control the Bluetooth device. Security reasons make it necessary to recognize specific devices, and thus enable control over which devices can connect to a given Bluetooth device.
  
  
• Advantages and Challenges of Designing with Multiple Inferencing Chips (Nov. 14, 2019)
  Using multiple inferencing chips can deliver significant improvements in performance, but only when the neural network is designed correctly
  
  
• Towards Self-Driving Cars: MIPI D-PHY Enabling Advanced Automotive Applications (Nov. 05, 2019)
  Since the invention of the automobile well over a century ago, car manufacturers have been focused on creating the highest-speed, safest, and most fuel-efficient cars possible.
  
  
• Data Over Sound: Encryption is Key (Oct. 28, 2019)
  You can send data over audio and it just might be more secure than using RF.
  
  
• Designing AI enabled System with SOTIF (Safety Of The Intended Functionality) (Oct. 21, 2019)
  Autonomous Vehicles (AV) needs more intelligence when it is on the move. The intelligence is not just an algorithm driven based on multiple sensor inputs alone, but here the intelligence need to be highly situational aware and by keeping the current vehicle dynamics. This needs lot situational and scenario based complex computation and communication with multiple Electronic Control Unit (ECU) within the vehicle.
  
  
• PUF: A Crucial Technology for AI and IoT (Oct. 14, 2019)
  One of the key challenges for AIoT is the protection of AI assets. AI functions often need to detect, evaluate and respond in real time. As a result, a critical security concern is the fact that internal databases and interfaces for AI are not suitable for encryption because such an operation would demand too much time and resources.
  
  
• IP Security Assurance Standard (Oct. 03, 2019)
  This paper introduces an emerging new standard called IP Security Assurance (IPSA) to address these concerns in a manner that is low-overhead, non-disruptive, and scalable across IP families. The standard specifies an approach to highlight IP assets and associated entries in the Common IP Security Concerns Enumeration (CIPSCE) knowledge base for the mitigation implementer to address.
  
  
• Implementing Secure Boot in Your Next Design (Sep. 30, 2019)
  The number of new viruses and malwares created every day is getting close to 1 million. Thus, in an always more connected world, getting protected against these attacks becomes absolutely critical. To make a device trustable one needs to make sure it runs only genuine firmware.
  
  
• How to Design SmartNICs Using FPGAs to Increase Server Compute Capacity (Sep. 26, 2019)
  An FPGA-based SmartNIC employs the expanded hardware programmability of FPGAs to build any data-plane functions required by the tasks offloaded to the SmartNIC. Because FPGAs are reprogrammable, the data-plane functions implemented by the FPGA can be torn down and reconfigured at will and in real time. All such offloaded functions operate at hardware – not software – speeds.