Industry Expert Blogs

All chip designs need some level of verification. This need has created an ecosystem of verification intellectual property suppliers (VIP), SystemVerilog users, and integration and EDA interoperability tool companies. System-Level Design discussed these issues with Dennis Brophy, Director of Strategic Business Development for the Design Verification and Test division at Mentor Graphics; Thomas Anderson, group director, verification product management and Ran Avinun, marketing group director for system design and verification at Cadence Design Systems; Neill Mullinger, product manager for verification IP, Michael Sanie, director of verification marketing and Frank Schirrmeister, director of product marketing, system-level solutions at Synopsys. What follows are excerpts of those discussions.

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