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55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process
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If ever EDA needed a ($700M) proof point on their value...IC Design Corner - Mike DemlerFeb. 02, 2011 |
As I reported yesterday, Intel announced that a “design error” in a SATA I/O support chip for the Sandy Bridge processor would cause them to respin the design… at a cost of $700M! From the information that Intel provided, it was apparent to me that the problem was most likely a voltage domain error, i.e. a low voltage device got accidentally hooked up to a higher voltage supply than it was spec’ed for.
A report on the internet today, if it is credible, confirmed my speculation:
quoting Intel’s Steve Smith (VP and Director of Intel Client PC Operations and Enabling) : The problem in the chipset was traced back to a transistor in the 3Gbps PLL clocking tree. The aforementioned transistor has a very thin gate oxide, which allows you to turn it on with a very low voltage. Unfortunately in this case Intel biased the transistor with too high of a voltage, resulting in higher than expected leakage current. Depending on the physical characteristics of the transistor the leakage current here can increase over time which can ultimately result in this failure on the 3Gbps ports.
Bingo! Exactly as I suspected. Intel’s comments yesterday:
