MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
Industry Expert Blogs
Don't listen to the experts. They have it backwards.The ESL Edge - Brian BaileyJun. 16, 2011 |
Let me take a stroll down memory lane. The year is 2009 and it is DAC. On a panel put together by Lucio Lanza, a long time EDA and semiconductor investor, they came to the conclusion that chips are costing $50-100M and that is too much. They said the return figures for EDA companies are even worse. They also said that if EDA could reduce those costs to $5-10M there would be an industry rebirth.
Also, remember that Gary Smith said (not sure if it was in 2009 or 2010) that cadence was no longer the top gun in EDA. The reason for this is that for the first time in history the bleeding edge customers were spending more than the early majority. Cadence had traditionally served this early majority market, but many of the top tier companies had now realized that by spending more on tools, and getting the best tools, they could compete better. Simply put, buying second rate tools made you a second rate company and there was little money to be made there.