Industry Expert Blogs

Having previously introduced the ARMv8-R architecture, it’s time to look more closely into its new technology and explain some of the benefits it will bring. I’ll try to convey the key concepts but I have to assume some familiarity with ARM architecture and Cortex processors such as ARM Cortex®-R5 processor.

 The most important addition in the ARMv8-R architecture is the Hypervisor mode which provides an additional level of privilege management in the processor hardware. Privilege Level governs what the currently running software can and cannot do with basic user tasks having the lowest level of privilege, i.e. Privilege Level zero or PL-0. An Operating System (OS) typically runs with higher privilege at PL-1 and is allowed to supervise things, for example, programming the interrupt controller or configuring the attributes for regions of memory and peripheral address map to police which user tasks are allowed to do what. Such policing is performed in hardware by a Memory Protection Unit, or MPU.

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