Industry Expert Blogs

I’ve been traveling in Europe popping into see various FPGA-based prototypers. It’s been a good week of lively discussion covering all aspects of prototyping from mapping RTL to prototype, to higher debug visibility and Hybrid Prototyping. At a number of these visits we discussed IP validation using the PCIe connected use model. I’ve discussed this use mode a number of times, in summary an IP block is placed in the FPGA-Based Prototype and then a PCIe end point core is used to memory map the IP across to a host machine. Typically the IP has a standard SoC bus interface such as AMBA so a bridge from AMBA to a PCIe core is used.

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