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Aeonic Generate Digital PLL for multi-instance, core logic clocking
Industry Expert Blogs
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How to reduce dynamic power by 50% for a MIPS CPUWith Imagination Blog - Alexandru VoicaSep. 25, 2014 |
Designing a CPU takes a lot skill and effort. Taking said CPU and reducing its dynamic power consumption by 50% takes a particular set of skills, skills one has acquired over a very long career.
After successfully delivering the first DOK for PowerVR Rogue GPUs, Imagination and Synopsys embarked on a second project that aimed at significantly decreasing power consumption for MIPS CPUs without sacrificing any of the leading performance numbers.
