MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
Industry Expert Blogs
Which IP for FD-SOI Ecosystem?SemiWiki - Daniel NenniDec. 08, 2014 |
We know that the best technology or product, even if it exhibits best in class and unmatched features, is almost of no use if lacking an ecosystem. If you think about a processor core, you will expect to find compatible communication bus and memories (inside the SoC) and operating system, compiler, debugger, etc. When dealing with a disruptive ASIC technology like FD-SOI, you will expect to have multiple sources for raw SOI wafers, at least double sourcing capability for processing these wafers and, last but not least, a solid IP ecosystem. If you can’t decree the creation of this IP ecosystem, you (the foundry or ASIC vendor) can certainly invest resource to internally develop the foundation IP (standard cell library or memory compiler). Your involvement in supporting or initiating the development of complexes IP by the best in class IP vendors will make the difference too.