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See Demonstration Video of PCIe 4.0 PHY IP in TSMC 16FF+Cadence IP Blog - Steven BrownMar. 01, 2016 |
Did you miss DesignCon this year? If so, you also missed the demonstration of our PCIe 4.0 PHY silicon. You can read more about the demo here.
The IP is implemented in TSMC 16FF+, and is in use by several customers to enable the next generation green datacenter. The underlying SerDes operates from 1.25Gbps to 16Gbps, and was shown supporting the PCIe 4.0 protocol. You can read more about the IP here.
And you can watch a video of the demo here.
