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Aeonic Generate Digital PLL for multi-instance, core logic clocking
Industry Expert Blogs
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TSMC: Technology UpdateBreakfast Bytes - Paul McLellanSep. 27, 2016 |
Twice a year TSMC has a big meeting in San Jose. These are the times that there is a public update on their process roadmap, how process ramps are going, the OIP ecosystem, and so on. But they make it hard for people like me since their rules are that they won't hand out the presentations, they won't let you take pictures of the screen, they won't let you video or record the presentations. But I'm allowed to take away anything that I can write down. Inevitably there are probably minor errors. So if you are wondering why this is so sparsely illustrated, that's the reason.
There were two presentations, one from Jack Sun on process technology and one from Cliff Hou on design technology Here's my summary of what they said.
