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The cache side channel vulnerabilities disclosed by security researchers recently have garnered much attention across the processor world. Here is information on the susceptibility of MIPS processor implementations to these techniques.

Scope

Given the extensive history of the MIPS architecture and breadth of usage across the industry, there are many varieties of MIPS processors being used across numerous markets and billions of products. The scope of this announcement applies to the analysis and findings on the licensable IP processor cores designed by, and available from, MIPS.

Scenarios

Many resources are now available that discuss these attacks, so the technical details of the mechanisms are not covered here. The websites that announced the vulnerabilities, specifically the Meltdown and Spectre pages, are a good starting point for general information and further details.

While all of the attacks are related to speculative execution of processor instructions that modify cache state and then infer information about memory contents, otherwise believed to be secure, via a side channel that can observe access timing, there are several variations that have been identified.

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