Aeonic Generate Digital PLL for multi-instance, core logic clocking
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Cadence Puts the IP in ...well, IPCadence on the Beat Blogs - Meera Collier, CadenceJun. 13, 2018 |
A lot has been written about AI and machinelearningdeeplearning, but a friend asked me, what does that have to do with Cadence, anyway? And what do you mean when you say, IP? I realized that I haven’t explained it yet. So here goes!
Tensilica Family of DSP IP
Imagine that you have a system like a home security system, and it has a sensor, like a camera. That camera is then connected to a central processing unit to interpret the data sent from the sensor, and then from that unit, action is taken based on how it interprets the data—unlock the door or call the police.
Seems pretty simple, right?
Well, here’s the thing. If we’re sending raw data to the central processing unit, your system must have two capabilities: the ability to send the data quickly to the central processing unit (that is, bandwidth) and a robust enough computer to not only determine friend from foe (AI) but also decide how it wants to react. Both of those aspects of the system can be incredibly expensive—both in terms of cost, and in terms of processing power (and, therefore, power power). And if your sensor is a radar or lidar unit, the “cost”, especially in terms of bandwidth, is even more!
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