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Aeonic Generate Digital PLL for multi-instance, core logic clocking
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How to extend the "unscalable" RISC architecturesCodasip Blog - Rupert Baines, CodasipFeb. 18, 2022 |
For many systems the best processor is one tailored for its task
A couple of years ago, Erik McClure (a Microsoft software developer, at the time) published a blog entitled, RISC Is Fundamentally Unscalable.
This blog was really quite interesting and made some very good points about the limitations of a pure RISC design.
THE LIMITATIONS OF A PURE RISC DESIGN
It takes me back: some of my first marketing tasks were around the religious war between RISC & CISC.
However, to a degree, I think Erik’s blog overstates things: nobody today really thinks of RISC-V as being just RISC.
That religious war is long-gone: we have all read Hennessy & Patterson, we all know to use quantitative technique and metrics to analyze performance and to make the inevitable trade-offs. Complex instructions, deeper pipelines, faster/cleaner architectures, power versus area versus performance – those are solved by modelling & data not simplistic binary divides or theological purity.
A key principle of RISC-V from its inception was the ability to add instructions, and there are a number of defined extensions, as optional modules.
There certainly are products using standard RISC-V cores with the standard base ISA. But there are many products with extensions. And for many applications you can do even better.
