English
NoC Silicon IP for RISC-V based chips supporting the TileLink protocol
Memory Characterization Focus on Yield Improvements
With rising mask cost and increasing design complexity, the ‘low-yield’ risks are becoming very critical for nanometer technology.
SANTA CLARA, Calif., June 2, 2005 – Legend Design Technology, Inc., a provider of circuit simulation and semiconductor IP characterization software, today announced that its industry-leading CharFlo-Memory! product, an automatic memory characterization tool, has been upgraded with new capabilities for improving silicon yields. The new release addresses the modeling optimization and reliability checks against signal integrity and noise-margin for embedded memories on system-on-chip (SoC) designs. It builds upon the market-leading position of CharFlo-Memory! product, offering the advantages of automation, performance, and accuracy in a fully integrated tool.
Legend’s memory characterization tool has been adopted by major foundries, IDMs and fabless design companies such as TSMC, UMC, Broadcom, Marvell and most Japanese semiconductor companies etc.. The timing and power models generated have been successfully proven in numerous SoC designs, including 65nm and 90nm technology.
With rising mask cost and increasing design complexity, the ‘low-yield’ risks are becoming very critical for nanometer technology. As a result, the market windows for the associated products could be totally missed. The newly released CharFlo-Memory! can prevent reliability problems and enhance design quality for improving silicon yields of memory IP, which occupy the majority of silicon areas. Yield improvements in the new release have been achieved by
1. Using the exact 'instance' characterization for various PVTs (Process, Voltage and Temperature) rather than just roughly interpolated or extrapolated from table models. The instance characterization has been critically required for 90nm and 65nm memory IP modeling.
2. Performing reliability check at circuit-level after recognizing the structures and patterns of memory designs. In memory characterization process, the model parameters have been optimized with the following constraints
• The signals need be stronger than the noise-margin (e.g. 100mv).
• The signals need be 'glitch' free.
• The signals need be 'meta-stability' free.
• The signals need be 'signal-integrity violation' free.
3. Enabling the 'layout parasitic RC extraction' by providing only critical nets to be extracted. Since the 'critical nets' is less than 1% of the total nets on chip, the time-consuming 'layout parasitic RC extraction' can be done in much shorter time. Furthermore, the circuit netlist extracted becomes much smaller, too.
The applications of using CharFlo-Memory! tool can be categorized for
1. Commercial memory-compiler users
At various PVTs (Process, Voltage and Temperature), CharFlo-Memory! can be used to automatically re-characterize the memory instances and generate the timing and power models in ‘.lib’ format at silicon-level accuracy. This ‘push-button’ flow supports all leading commercial memory compilers from 0.25um to 90nm technology.
2. In-house memory-compiler or custom-memory development
CharFlo-Memory! can be used for both detailed design verification and yield-oriented characterization. Either the accurate instance model or table-lookup compiler model can be automatically generated. Even for nanometer memory designs, the modeling accuracy and silicon yields have been fully verified in production at major foundries.
CharFlo-Memory! tool with new capabilities for improving silicon yields is available now from Legend Design Technology, Inc.
About Legend
Legend Design Technology Inc. is a leading provider of circuit simulation and semiconductor IP characterization software for SoC designs. With an emphasis on productivity and value, Legend’s CharFlo-Memory! toolset revolutionizes the time-consuming and error-prone processes associated with characterization. MSIM is Legend’s high-accuracy SPICE circuit simulator with great convergence and extensive model support. Turbo-MSIM is Legend’s high-speed and high-capacity circuit simulator ideal for timing and power simulation, and function verification. Both simulators are well designed for nanometer technology challenges, and provide excellent price performance. For more information, visit www.LegendDesign.com.
###
CharFlo-Memory! and Turbo-MSIM are trademarks, and MSIM a registered trademark of Legend Design Technology, Inc.
SANTA CLARA, Calif., June 2, 2005 – Legend Design Technology, Inc., a provider of circuit simulation and semiconductor IP characterization software, today announced that its industry-leading CharFlo-Memory! product, an automatic memory characterization tool, has been upgraded with new capabilities for improving silicon yields. The new release addresses the modeling optimization and reliability checks against signal integrity and noise-margin for embedded memories on system-on-chip (SoC) designs. It builds upon the market-leading position of CharFlo-Memory! product, offering the advantages of automation, performance, and accuracy in a fully integrated tool.
Legend’s memory characterization tool has been adopted by major foundries, IDMs and fabless design companies such as TSMC, UMC, Broadcom, Marvell and most Japanese semiconductor companies etc.. The timing and power models generated have been successfully proven in numerous SoC designs, including 65nm and 90nm technology.
With rising mask cost and increasing design complexity, the ‘low-yield’ risks are becoming very critical for nanometer technology. As a result, the market windows for the associated products could be totally missed. The newly released CharFlo-Memory! can prevent reliability problems and enhance design quality for improving silicon yields of memory IP, which occupy the majority of silicon areas. Yield improvements in the new release have been achieved by
1. Using the exact 'instance' characterization for various PVTs (Process, Voltage and Temperature) rather than just roughly interpolated or extrapolated from table models. The instance characterization has been critically required for 90nm and 65nm memory IP modeling.
2. Performing reliability check at circuit-level after recognizing the structures and patterns of memory designs. In memory characterization process, the model parameters have been optimized with the following constraints
• The signals need be stronger than the noise-margin (e.g. 100mv).
• The signals need be 'glitch' free.
• The signals need be 'meta-stability' free.
• The signals need be 'signal-integrity violation' free.
3. Enabling the 'layout parasitic RC extraction' by providing only critical nets to be extracted. Since the 'critical nets' is less than 1% of the total nets on chip, the time-consuming 'layout parasitic RC extraction' can be done in much shorter time. Furthermore, the circuit netlist extracted becomes much smaller, too.
The applications of using CharFlo-Memory! tool can be categorized for
1. Commercial memory-compiler users
At various PVTs (Process, Voltage and Temperature), CharFlo-Memory! can be used to automatically re-characterize the memory instances and generate the timing and power models in ‘.lib’ format at silicon-level accuracy. This ‘push-button’ flow supports all leading commercial memory compilers from 0.25um to 90nm technology.
2. In-house memory-compiler or custom-memory development
CharFlo-Memory! can be used for both detailed design verification and yield-oriented characterization. Either the accurate instance model or table-lookup compiler model can be automatically generated. Even for nanometer memory designs, the modeling accuracy and silicon yields have been fully verified in production at major foundries.
CharFlo-Memory! tool with new capabilities for improving silicon yields is available now from Legend Design Technology, Inc.
About Legend
Legend Design Technology Inc. is a leading provider of circuit simulation and semiconductor IP characterization software for SoC designs. With an emphasis on productivity and value, Legend’s CharFlo-Memory! toolset revolutionizes the time-consuming and error-prone processes associated with characterization. MSIM is Legend’s high-accuracy SPICE circuit simulator with great convergence and extensive model support. Turbo-MSIM is Legend’s high-speed and high-capacity circuit simulator ideal for timing and power simulation, and function verification. Both simulators are well designed for nanometer technology challenges, and provide excellent price performance. For more information, visit www.LegendDesign.com.
###
CharFlo-Memory! and Turbo-MSIM are trademarks, and MSIM a registered trademark of Legend Design Technology, Inc.
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