Networking concepts inspire next-gen SoCs

Margaux, France — Your office computer network may be a model for next-generation IC designs, said system-on-chip experts who gathered in this small village in the French wine country last week.

Interest in the notion of networks-on-chip was high at the Multi-Processor SoC Conference (MPSoC), as the daytime technical sessions morphed during the evenings into spirited multilingual discussions over dinner. Among the presenters were French startup Arteris SA, which claims to offer the first commercial NoC tools, and Sonics Inc., which now says the "smart interconnect" it introduced back in 1999 was in fact an NoC concept.

The conference did not produce a consensus definition of the NoC itself, and skepticism about potential trade-offs was rife. But there was clear consensus on one point: On-chip interconnect is a bottleneck. Point-to-point buses simply can't keep up with the bandwidth that's required for the processors, memories and intellectual-property (IP) blocks on complex SoCs.

The NoC concept replaces the fixed bus with a packet-based approach and a layered methodology — for example, a transaction layer, transport layer and physical layer. It brings such networking ideas as quality-of-service (QoS), which involves the ability to predict latency and the arrival of packets, down to the chip level.

"Instead of a dedicated wire for each connection, we reuse wire resources based on a three-layer packet network," said Charles Janac, newly appointed CEO of Arteris, which unveiled its NoC tools as configurable IP in March. "We're scheduling the delivery of packets across the same wires."

The potential advantages, proponents say, include dramatically faster data transmission rates, more flexibility and easier IP reuse.

Arteris CTO Alain Fanet said the company's NoC approach addresses the IP reuse problem because it can easily connect IP that uses different bus formats. Its reconfigurability just might save a silicon redesign, he said. And to those MPSoC participants who expressed concern about the NoC's potential to increase power consumption and area, Fanet responded that die size could in fact be reduced, given that conventional buses take up space with FIFOs and repeaters.

Both Arteris and STMicroelectronics define an NoC as a flexible, scalable, packet-based on-chip network. But Sonics CTO Drew Wingard has a simpler definition: NoCs, he said, are chips that "apply networking techniques to on-chip communication."

The recent SonicsMX product, he said, is an NoC that utilizes socket-based design, optimized fabric protocols and higher-level services, including QoS, power management and security. But its "packets" are actually single words, and SonicsMX does not use the globally asynchronous, locally synchronous (GALS) approach of Arteris and many current research efforts.

"A lot of people have proposed NoC as a solution to chip interconnect," observed Wayne Burleson, associate professor of electrical and computer engineering at the University of Massachusetts at Amherst. "It's a nice step in the right direction, but there are still a lot of design decisions to be made." Among them are the granularity of cores, bus width, network topology and what should be asynchronous or synchronous.

Global and on-chip networking
Martina Zitterbart, professor at the Institute for Telematics at Karlsruhe University (Germany), noted that a number of concepts in her world apply to NoCs, including packet switching, flexibility, robustness, security and QoS. While "zero touch" global networks that don't require human intervention are a goal, she said, in the case of on-chip networks — which aren't going to come with network administrators — zero-touch is a mandate.

STMicroelectronics has developed a technology, called STNoC, that can support any topology and be automatically generated with an internal tool, said Marcello Coppola, head of ST's Grenoble, France, research lab.

"We would certainly like to use NoCs," commented Coppola's ST colleague, Pierre Paulin, director of SoC platform automation technologies at the company.

Kees Goossens, principal research scientist at Philips Research, is working on NoCs and is most concerned about memory. "You can move data around, but where are you going to store it?" he asked. As for memory hierarchy, Goossens said NoCs work well with architectures that involve streaming and "struggle" with other architectures.

Giovanni de Micheli, professor at the Ecole Polytechnique Federale in Lausanne, Switzerland, presented some benchmarks from xpipes, a synthesizable NoC infrastructure from the University of Bologna (Italy) and Stanford University. Compared with an Amba AHB multilayer bus, xpipes showed up to 21 percent better execution time under heavy system contention, even though its latency is a bit worse.

"You can achieve significant performance with an NoC, but the area and power overhead is still significant," de Micheli said.

Another academic benchmark, presented by Norbert Wehn, professor at the University of Kaiserslautern (Germany), compared fixed interconnect and NoC approaches for a low-parity density check decoder. The NoC ran at 500 MHz, vs. 64 MHz for the fixed bus, and was much more flexible.

The bad news: The NoC consumed 30 watts vs. 700 mW for the fixed bus, and had twice the die size.

Given the performance and area trade-offs, Wehn considers NoC to be "hype" that may have difficulty finding applications.

Commercial efforts, however, claim to be doing much better. Arteris says there may actually be a die size savings with its approach and claims the power consumption is no worse than for conventional bus structures.

The SonicsMX, meanwhile, currently going into mobile-handset applications, has sophisticated power-management capabilities; indeed, Sonics claims power efficiency as a feature.

Coming to market
SonicsMX was introduced last year, with Texas Instruments Inc. and Toshiba Corp. as announced customers, and Wingard said tapeouts have already occurred. Arteris' NoC design tool kit is currently undergoing evaluations.

The Arteris configurable IP is delivered through two products: the NoC Explorer, which is used to design a network topology, and the NoC Compiler, which takes the topology and produces SystemC simulation models and synthesizable RTL.

The technology includes a transaction layer, which provides a reconfigurable IP interface; a package transport layer, which promises flexibility and wire efficiency; and a physical layer based on GALS. Arteris claims maximum throughput of more than 750 MHz, compared with 250 MHz for buses. "We offer three to four times better efficiency than any bus today," said Fanet.

The technology employs network interface units that bring IP into locally synchronous "clusters" controlled by switches. Global nets are asynchronous. This strategy is used, said Janac, because a fully synchronous system creates long wires. A fully asynchronous system is difficult to implement, he said.

SonicsMX, meanwhile, builds on the company's smart-interconnect concept, introduced with its SiliconBackplane in 1999. That offering was a layered system using a distributed, shared bus. SonicsMX adds a crossbar switch, separate request and response networks and higher throughput, specified at 200 MHz at 90 nanometers but with the potential to go much higher, Wingard said.

SonicsMX offers packetization, Wingard said, although the packet size is typically one word. Bigger packets, he said, must be stored in big buffers. The approach supports asynchronous boundaries but is otherwise synchronous; GALS, according to Wingard, requires custom design or improvements in EDA tools.

So what makes SonicsMX an NoC? Wingard pointed to the use of "intelligent agents" — the units that link the interconnect to the IP — and the high-level services they offer, including power management, security, and both guaranteed and best-effort QoS. The power-management feature can shut down portions of the chip that are not active, and it supports multiple voltage islands. The security manager checks access attempts, flags violations and transports security identification.

From Wingard's perspective, Arteris' approach, lacking such power, security and QoS services, is "bare bones." He said it remains to be seen whether the company's high-throughput claims will hold up in memory-dominated systems.

Janac conceded that Sonics offers more power-management features and acknowledged that Arteris supports best-effort QoS only. But he argued that Arteris' approach is faster, more configurable and independent of the Sonics-derived OCP protocol, although Arteris does support it.

It takes two
And with Arteris focusing on networking and Sonics on mobile handsets, the companies are chasing different markets. "We don't really compete now, although we may in the future," Janac said. "That's all right. A healthy market needs two players."

To that emerging market, Philips' Goossens would add a dose of realism "NoC is not a panacea," he said. "It's just another tool in the toolbox of system designers.

"You can't just expect to make IPs, connect them to a magic box and have everything work."