Tamper-Resistant Dual 8051 Multi-Controller Mates With Freescale 4-MBit (256K x 16) MRAMs

AUSTIN, Texas, October 12, 2005 – Silicon Laude (pronounced “laudee”) announces the availability of the world’s first, and only, tamper-resistant, Dual MCS8051 instruction-compatible multi-controllers that can directly interface with Freescale’s new MR2A16A 4-Mbit (256k x16) MRAMs.  Dubbed the SL80C051-2001 for the tamper-resistant version, and SL80C051-2002 for the lower-cost, non-tamper-resistant version, the Dual8051 multi-controllers can substantially reduce component count, minimize PCB board space, and improve overall processing performance, all while warding off attacks from software and data pirates in embedded applications that require secure data collection and storage.  With its small, 13mm x 13mm, 144-ball FBGA packaging and non-DES cryptographic engine, the SL80C051-2001 multi-controller is ideal for use in embedded applications such as financial data terminals, personal identification number (PIN) pads, and other similar applications where a high level of security from data/software pirating is a priority.  The lower-cost, non-secure SL80C051-2002 device is also available for general-purpose 8051 multi-controller applications that do not require such a high level of security.

Dual8051 CPU Architecture

Both devices are based on a parallel pipeline architecture that is capable of instruction execution speeds of up to 25 MIPS when used with one or more 20ns, Freescale MR2A16A MRAM(s), or up to 11 MIPS when used with one or more SST 32HF202 Flash + SRAM combo memories or traditional NVRAMs.  Sharing a common program counter (PC) output register and 16-bit external program/data bus, both of the on-board MCS8051 instruction-set-compatible CPUs are completely autonomous, in that they can operate independently from one another, or be made to respond to a dedicated internal interrupt line for parallel processing/controller applications.  Because each CPU shares a common external program/data memory of up to 2 megabytes using their own extended addressing windows, they can process and pass large amounts of data between each other without actually have move the data.  This saves an enormous amount of processing cycles, resulting in a higher multi-processing throughput capability not found on any other 8051-type microcontroller.

Cryptographic Engine

To discourage tampering by would-be data and software pirates, the SL80C051-2001 version incorporates several features that, together, make software and data piracy extremely difficult, if not impossible.  These features include a proprietary, non-DES, cryptographic engine implemented in hardware, hidden interrupt vectors, and a shared, 16-bit program/data bus.   Because the two CPUs share the same external address and 16-bit data bus, there is virtually no way to determine which CPU is fetching an instruction or reading data on any given clock cycle.  Moreover, even if the would-be pirate knew the cipher, there is virtually no way to determine, using external means, which of the 16-bits belongs to which CPU, or which of the 16-bits belongs to a given 8-bit data being moved over the external bus.

To enable the security function, each device comes with its own key already programmed into it, which the cryptographic engine uses to encipher and decipher all movements in and out of external memory.  Also, on power-up or reset, the device will not execute instructions if it determines that the program has been tampered with.  Finally, since there are two CPUs available, one can be used to run the primary application, and the other can assume counter attack duties such as continually scanning the external memory for indications of tampering, such that, if found, it can assert and hold the other CPU in a reset state before setting its own power down bit in its PCON register.

Hardware Monitor and Data Exchange

100% instruction-set-compatible with the MCS8051 microcontroller, the devices are fully supported by the Keil Software 8051 C compiler and uVision IDE, as well as Domain Technologies BoxView real-time, high-level language debugger and USB-JTAG debug pod.  On-chip hardware monitor and data exchange debugging functions include unlimited software breakpoints, single-steps, program and data memory downloads, and on-the-fly register/memory examination and editing.  With Silicon Laude’s proprietary Hardware Monitor and Data eXchange (HMDXTM), applications developers are able to monitor and exchange data between host computer and multiple targets on-the-fly, and in real-time, without first having to breakpoint or otherwise halt the microcontroller.  This capability is especially useful for tweaking constants and/or variables in program/data memory, or simply watching a sine or arbitrary waveform modulate in real-time when the window is opened in graphic animation mode.  Because all data and program transfers are done in hardware, no monitor software routines are required on the target side to support HMDX.

With orders being accepted now, and deliveries starting in first quarter 2006, the SL80C051-2001 is priced at $60.00 each, while the SL80C051-2002 is priced at $45.00 each, both in 100-unit quantities.  Each order will be shipped with a unique security key already programmed into each device.  For orders of 1000 units or more, Silicon Laude can provide customized versions of the Dual8051 multi-controller.  For pricing information on a customized Dual8051 multi-controller, please contact Silicon Laude.  Advance information on the Dual8051 multi-controller is available for download at the  www.siliconlaude.com website.

About Silicon Laude

Silicon Laude  is a privately held, fabless semiconductor company headquartered in Austin, Texas.  Formed in 2005, Silicon Laude is primarily a service-oriented company specializing in low-to-medium volume and quick-turn production of standard and customized microcontroller IC designs for select customers.  At present, all of Silicon Laude's customized microcontroller designs are based on a patented 8051-type architecture that enables true, real-time monitoring and debugging of software applications using a zero-software-overhead monitor that is implemented in hardware and accessible via an IEEE 1149.1- compatible connection.