Xtensa 6 Processor Core Provides Fastest Customization Path, Lower Power and Advanced Security Provisions

Update: Cadence Completes Acquisition of Tensilica (Apr 24, 2013)

Algorithm to Fully Configured Core in Less than One Hour

Santa Clara, Calif. – October 24, 2005 – Tensilica, Inc., today announced a new version of its Xtensa processor family – the Xtensa 6 configurable and extensible processor core for system-on-chip (SOC) design. As a replacement for Tensilica’s workhorse Xtensa V processor, Xtensa 6 adds three major enhancements: the ability to automatically customize it from a C/C++ based algorithm using Tensilica’s proven XPRES Compiler; approximately 30 percent lower power than Xtensa V; and advanced security provisions in MMU-enabled configurations through a “no execute” bit that provides enhanced protection against malicious code.

“Xtensa 6 provides SOC designers with the fastest, most cost-effective SOC block design tool in the industry,” stated Steve Roddy, vice president of marketing, Tensilica. “By using our popular XPRES Compiler, in less than an hour designers can create application-specific building blocks that can serve as either conventional control processors or as a suitable alternative to RTL-based hardware block design, but in a fraction of the time and without the verification headaches. We expect this product to significantly widen our customer base because it fully automates time-and-resource intensive IC design steps and adds programmability to the post-silicon design, a crucial value-add enabler in fast-moving, high-volume SOC markets.”

Automatic Configurations from C/C++ Code

Tensilica’s XPRES Compiler enables the rapid development of optimized SOC building blocks without requiring designers to hand code their hardware using design languages like VHDL and Verilog, which take months of design and verification effort. Instead, designers input the original algorithm that they’re trying to optimize, written in standard ANSI C/C++, and the XPRES Compiler, coupled with Tensilica’s automated processor generation technology, automatically generates an RTL (register transfer level) hardware description and associated tool chain.

The XPRES Compiler automatically determines which functions should be accelerated in hardware and generates a comprehensive hardware/software solution for those functions. No RTL coding is required; the XPRES Compiler automatically generates the necessary RTL code that is pre-verified to be correct by construction.

In less than an hour, the resulting hardware block is delivered electronically in the form or a pre-verified Xtensa 6 processor core that has been optimized for that exact application. The correct-by-construction-generated RTL removes the verification headaches associated with hand-generated, non-programmable hardware blocks.

The XPRES Compiler allows designers to quickly evaluate different configurations and make area/speed/power trade-offs. It also preserves C code portability, generating Xtensa 6 processors that can be re-used over a range of similar application software code. Similar code can take advantage of the acceleration without any modification due to the automatically generated C/C++ compiler associated with that particular configuration. Additionally, the XPRES Compiler also works with Tensilica’s flagship Xtensa LX processor, meaning that XPRES Compiler users can rapidly explore a wide range of hardware alternatives.

Lower Power for Handheld Applications

Tensilica significantly improved the base architecture of the Xtensa 6 processor, resulting in a 25-30 percent improvement in power dissipation. Several techniques were employed. Tensilica used both fine-grain clock gating, which turns off power to small sections of the processor when not in demand, and coarse-grain clock gating, which conserves power throughout much larger portions of the chip. For example, when a processor activity such as a cache-line fill occurs, coarse-grain clock gating is activated, saving valuable power.

Advanced Security Provisions

In this newest member of the Xtensa processor family, Tensilica employs advanced security provisions in the Xtensa MMU (Memory Management Unit) configuration option similar to what AMD and Intel have provided for personal computers. While AMD calls the feature Enhanced Virus Protection (EVP) and Intel calls it eXecute Disable (XD), it is generically known as NX for No eXecute. NX provides the ability to protect portions of memory so processor instructions can’t execute in those areas. In Xtensa 6 configurations that employ the full virtual memory capability of the Xtensa MMU, the new security features of the Xtensa 6 design set some areas of memory off bounds, thus helping to prevent worms and other types of malicious code from executing functions.

This feature will be of interest to designers planning to run the embedded Linux operating system on Xtensa 6 processors, as this feature will be incorporated in future versions of the Linux operating system.

Pricing and Availability

Tensilica’s new Xtensa 6 processor is available now. Licensing fees for a single processor configuration with perpetual usage rights start at $350,000.

About Tensilica

Tensilica was founded in July 1997 to address the growing need for optimized, application-specific processor solutions in high-volume embedded applications. With a configurable and extensible processor core called Xtensa, Tensilica is the only company that has automated and patented the time-consuming process of generating a customized processor core along with a complete software development tool environment, producing new configurations in a matter of hours. For more information, visit www.tensilica.com.