Adaptive Silicon preps FPGA core for ASICs

Adaptive Silicon preps FPGA core for ASICs
By Craig Matsumoto, EE Times
October 10, 2000 (12:50 p.m. EST)
URL: http://www.eetimes.com/story/OEG20001010S0027

SAN MATEO, Calif. — Adaptive Silicon Inc. has received first silicon on its programmable ASIC cores and is lining up licensees in preparation for an early 2001 launch.

Adaptive Silicon (Los Gatos, Calif.) doesn't expect to release products until March, and its initial sales will be to ASIC customers of LSI Logic Corp., its primary investor. But Adaptive Silicon (ASi) has begun porting its cores to the manufacturing processes of foundry Taiwan Semiconductor Manufacturing Co. (TSMC) and eventually hopes to license its cores broadly through the ASIC and foundry communities, and eventually to systems providers themselves.

"In the short term, our objective is just to get customers into production in the first half of next year at LSI," said Ralph Zak, vice president of marketing at ASi.

ASi first drew notice a year ago when LSI Logic revealed plans to provide small programmable cores of less than 50,000 gates inside its ASICs. The idea of combining standard-cell logic with a programmable array has been a hot topic in the semiconductor industry, most notably among FPGA suppliers, who have begun attaching fixed-function cores to programmable arrays.

But FPGA vendors have been espousing devices that contain large amounts of programmable logic. ASi is developing small cores — typically well under 30,000 ASIC gates — that would represent upgradeable or unfinished sectors of a system-level chip. ASi claims its products will be the first of their kind to hit the market, with only Actel Corp. (Sunnyvale, Calif.) having announced plans to produce programmable ASIC cores.

The real need for programmability lies in the 10,000-to-15,000-gate range, ASi officials contend. "Engineers are only creating RTL in chunks of that size," Zak said. "People don't tend to do 100,000 gates in a chunk."

ASi's Programmable Logic Cores (PLCs) consist of a hard core containing the programmable array and a set of soft-core adapters to connect to various interfaces or buses.

The basic unit of the hard core is the quad block, which equates to roughly 1,500 ASIC gates. Quad blocks can be tiled into small arrays called hex blocks, the largest being 4-by-4 for the first generation of PLCs. Larger arrays are possible but might not have enough routing to support all the quad blocks, ASi officials said.

Inside each quad block are four 4-bit arithmetic logic units. They can be used as ALUs or treated as independent three-input lookup tables, depending on how they are programmed; the distinction is made between the synthesis and mapping steps, said Tim Garverick, president and chief operating officer of ASi.

Two sets of tools are being developed at ASi — one to integrate PLCs into a standard ASIC flow, and one to design and program the PLC itself. The former tools will input PLC data, such as timing information, into standard EDA tools.

"We need to feed into the existing ASIC flows all the views, all the formats, all the data that they need to work with their tools," Garverick said.

ASi also is developing tools for programming the PLCs, as well as tools for programming and mapping the PLCs themselves. Typically, designers will have to iterate between the two sets as the PLC and ASIC begin affecting one another in areas such as timing.

ASi hopes to license its cores to ASIC vendors, but foundry business is also in the cards for ASi, where manufacturers such as TSMC might own a license to build ASi cores into customers' chips. Foundry licenses would help ASi get better distribution but aren't being pursued just yet, Zak said.

"Long term, we would be interested in that. Short term, it might not be practical," said president Garverick.

For now, ASi is in its early stages. The company received its first test chips back from LSI Logic in the last days of Sept ember, and it doesn't expect to have any production-worthy product until early next year.

ASi also has begun its first foundry port, to the processes of TSMC, but hopes to get the cores ported to all the major foundries' processes. Each port is a relatively simple procedure that "takes three or four people three to four months," Zak said.

In the long run, ASi also might begin licensing cores directly to systems providers for their in-house ASICs. One systems company already has approached ASi about this possibility, Zak said.

ASi hopes to release new core architectures every 18 to 24 months. In addition to allowing larger sized blocks, future architectures might be more application-specific; for example, a DSP-oriented core might sacrifice some flexibility for greater density, Garverick said.

In addition, ASi envisions teaming up with system vendors or IP providers to develop hybrid parts, combining a PLC with a fixed-function block such as a bus interface or microprocessor. These parts, whi ch at least superficially resemble the ASIC-FPGA hybrids being discussed by programmable logic vendors, could be jointly marketed by ASi and its partner in each case, Zak said.

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