Is system-level the next wave in EDA tools for SoCs?

Is system-level the next wave in EDA tools for SoCs?
By Tets Maniwa, EEdesign
August 21, 2000 (11:15 a.m. EST)
URL: http://www.eetimes.com/story/OEG20000821S0016

As we move ever closer to the realization of systems on silicon, we have to distinguish between the technologies and capabilities of the tools for "just a larger chip" and true system-level design tools. The 10-year cycle of tool generations suggests we are due for another major change, as big as the change from schematics to HDLs in the late 1980s and early 1990s.

Systems require architectural exploration and evaluation. The greatest opportunity to affect power consumption and performance come at the system-architecture level and not at the device-implementation level. To date, all of the IC design tools have focused on getting more gates into a defined area, and optimizations through synthesis only change the speed-area-power variables by 10 percent to 15 percent. As we move into the nanometer processes the optimizations to minimize gate counts tend to become increasingly irrelevant, except for the block-level design work.

Some of the decisi ons at the system level will affect more than just the IC. For example, choosing to put a function into software may cause memory to move to an external chip because the memory requirements exceed the available on-chip capacity. The external memory will increase power consumption and decrease overall system performance. It also makes the printed-circuit-board design much more difficult. That's because the myriad high-speed lines and buses demand constraint-driven traces as much as the IC layout requires timing-driven place-and-route to meet specifications.

In addition to the tools for IC design and implementation, the system-level design also needs a way to evaluate the tradeoffs in architectures as well as in hardware and software partitioning. The ideal process would provide analysis of the desired parameters-performance, power and others-and in addition would generate an executable specification for use in the verification phase so that the final implementation could be checked against the original fu nctionality.

Some early generation tools helped with the hardware-software verification and integration, and some new tools are working on the early design. CoWare Inc. has a system-level design tool that has the basic exploration and analysis functions in place, and its latest release has added capabilities for platform-based design. The software not only helps to evaluate the internal structures and partitioning, but also generates the interface logic that glues the platform blocks together. As you move blocks around and change hardware and software partitions, the design tool makes the necessary changes in the interface logic to keep the system functioning. The outputs are an executable specification, an optimized architecture and synthesized interfaces among the various hardware and software blocks.

But there is a missing link in this function- and platform-based design approach: the lack of models of the various blocks. Unfortunately, the number of views and levels of accuracy for a set of mod els for a virtual prototype differ as a function of the level of detail at the moment. For the initial explorations, fairly simple and fast models are useful. As the details of the design and the specifications become refined, the instruction set simulator and the basic memory model become inadequate and are replaced by bus-functional models or cycle-accurate models. Generating the whole family of models is a major challenge for the design community, whether internal groups or outside vendors of intellectual property.

This lack of full sets of models tends to restrict the choices of components to those already available, and precludes the complete exploration of the design space. Even though the design tools are starting to show up and address the matters of system-on-chip and platform-based design, the designers' jobs are still difficult because all of the pieces are not yet in place. The big semiconductor companies and system houses have marginal repositories with limited internal and external IP. The realization of SoC designs will depend upon a mixture of higher level tools and the libraries of components to avail ourselves of the potential creativity locked up within the designers' heads.