Compiler shortens DSP design time, startup claims

Compiler shortens DSP design time, startup claims
By Stephan Ohr, EE Times
August 10, 2000 (3:13 p.m. EST)
URL: http://www.eetimes.com/story/OEG20000810S0021

SCHAUMBURG, Ill. — Mach Design Systems, a startup, claims to have "cracked the code" for synthesizing DSPs using C code from the Matlab simulator of The Mathworks Inc. Based on a compiler developed at Northwestern University, Mach Design said it can convert Matlab code into register-transfer level (RTL) VHDL that can be used to synthesize ASICs or FPGAs. The compiler can also generate C code that can execute on general-purpose embedded processors, said Prith Banerjee, president and chief executive officer of the new company.

Incorporated on July 18, Mach Design is close to completing venture financing, said Banerjee, the Northwestern professor who headed the compiler development project. The startup includes a number of software developers from Northwestern, and will have offices in both Chicago and San Jose, Calif. Alok Choudhary will serve as vice president in charge of research, contracts and services.

Banerjee and Choudhary, along wit h professors Nagaraj Shenoy, Scott Hauck and students in the Electrical and Computer Engineering Department at Northwestern, developed the Matlab compiler under a grant from the Adaptive Computing Systems Program of the Defense Advanced Research Projects Agency (Darpa). The Mach Design principals have filed for several patents based on their project work, and are pursuing an exclusive license for the technology from Northwestern.

The company will develop a system-level EDA tool called Mach (Matlab compiler for high-level design) that will take high-level descriptions of embedded applications written in Matlab and automatically produce code for execution on general-purpose processors such as Texas Instruments Inc.'s C40 DSP and Motorola's PowerPC, and on FPGA or ASIC hardware implementations.

The Mach compiler will address the time-to-market considerations of manufacturers developing new Internet, wireless, 3G or voice-over-IP designs, Banerjee said. It will reduce the process of converting Matlab code to synthesizable RTL from one month to less than one hour in some cases, he said.

Matlab from The Mathworks (Natick, Mass.) is arguably the most popular simulator for analyzing block-level DSP algorithms. It is used by more than 400,000 designers in 100 countries and at 2,000 universities, Banerjee said. Its application for digital signal processing include the testing of algorithms for image processing, communications protocols, and motion control.

But the C code Matlab uses can neither synthesize a new DSP hardware block, nor be used to program a general-purpose DSP. In fact, Matlab C does not mesh readily with the new-generation of C synthesis tools from companies like Synopsys Inc. and Frontier Design. Over the years, a number of EDA tool vendors have proposed synthesis links to Matlab to ease the implementation of DSP functions in FPGAs and ASICs, while Motorola recently joined with TI to promote code generators for its DSPs that stem from Matlab and SimuLink instructions. But the goal of generating new DSPs from high-level Matlab instructions has remained elusive.

Developed in 1984, the Matlab language provided a more powerful and productive computation environment than Fortran, C and C++, said Banerjee. Its easy-to-use, interpretive environment contributes to its popularity, and users need not declare variables for types, shapes, or sizes. But without spelled-out variables, designers must manually translate the Matlab algorithms into RTL VHDL for hardware implementations in FPGAs or ASICs, and that process can take several months, Banerjee said. The goal of the Darpa-funded research was to take Matlab and have it map automatically on a network of heterogeneous processors or reconfigurable logic.

The result was Match (Matlab compiler for heterogeneous computing systems), a mechanism for parsing Matlab programs into intermediate representations. In operation, it builds what Banerjee calls a data and control dependence graph . It automatically identifies areas for fine-grain, medium-grain, and coarse-grain parallelism. In its final operations, it maps operations to multiple FPGAs, multiple embedded processors and multiple DSP processors. Thus, the compiler includes automatic parallelization, scheduling, and program mapping.

An add-on feature would enable the compiler to compare Matlab functions implemented in custom logic with those implemented on general-purpose hardware. Space-time adaptive processing radar algorithms and an MPEG decoder were used to benchmark the data flow graphs in the compiler. "In each benchmark, we studied the solution to the problem for various combinations of through-puts and latency constraints," Banerjee said. "In each case the compiler gave the right solutions in terms of the number of pipeline stages used. It gave better solutions than a hand-optimized solution in most cases by about 10-to-20 percent in terms of the cost of the solution in dollars," he said.