Low-cost embedded VLIW platform under construction

Low-cost embedded VLIW platform under construction
By Alexander Wolfe, EE Times
August 7, 2000 (3:31 p.m. EST)
URL: http://www.eetimes.com/story/OEG20000807S0030

NEW YORK — Aiming to ready economically priced, VLIW embedded processors for tight time-to-market applications, Hewlett-Packard Labs and STMicroelectronics have teamed up on the Lx, a platform they plan to unveil this fall at the Microprocessor Forum.

"The fundamental thing we believe is that at any level of technology, we can produce a very long-instruction-word processor that's two to 10 times faster than an equivalent RISC processor," said Roger Shepherd, manager of advanced architectures at STMicroelectronics' Bristol, England, labs. Shepherd also serves as STM's lead representative on the project at HP Labs (Cambridge, Mass.).

Shepherd confirmed that work is proceeding apace and that a formal announcement is planned for the forum, which will convene in October in San Jose, Calif.

The Lx family is intended to be used in system-on-chip (SoC) configurations, where it can be married with appropriate additional processor capabilities an d desired peripherals. It's certainly not being touted as a general-purpose microprocessor, which requires a notoriously expensive infrastructure of development tools. One possible app would be a set-top box, where the multiple Lx cores could be configured on a single chip to handle, for example, general-purpose processing, MPEG decoding and streaming media data types.

Although HP and ST do not like to use "DSP" to describe the Lx — "DSP is too specialized," they write — the new platform is perhaps more DSP-like than anything else. (Strictly speaking, the companies see the Lx as a convergence of DSP and microcontroller.)

Indeed, the Lx prototypes that are due by year's end will enter a DSP market that has been flooded by new devices and has become a testbed for everything from reconfigurable computing DSPs to VLIW design. Competitors will likely run the gamut from high-flying upstarts such as the configurable-core chips from Tensilica to such VLIW DSPs as Motorola's StarCore, TI's C6 and P hilips' Trimedia. Also sure to remain in the mix are tried-and-true general-purpose platforms such as MIPS and ARC.

In practical terms, the Lx work appears to go far beyond technology that HP first touched upon in a December 1998 talk at the MICRO-31 conference. There, HP laid out its vision of the Pico (program in, chip out) Architecture Synthesis System, a proposed set of automated software tools that HP believed could make it economically feasible to roll custom processors quickly, in low volumes, for specialized, deeply embedded applications.

But the Pico concept was based on an architecture akin to HP's and Intel's highly advanced IA-64 architecture (a.k.a. Merced). The Lx delivers a lighter load, in terms of power consumption and complexity.

Nevertheless, in offering the ability to turn complex embedded requirements — for low power consumption and high Mips — into custom chips, HP and STM would push far beyond today's SoC approach. Lx custom processors would be architected by an a utomated hardware/software co-design process. The chips would be churned out in very low volumes for specific, deeply embedded applications.

A major impetus for the venture is a perceived need to supply the burgeoning demands of smart embedded devices such as Web processors, automotive navigation systems and other new-age consumer-electronics devices being suggested by Internet designers.

The first peek at the Lx project came in June, when engineers from the two companies delivered a paper on the effort at the 27th Annual International Symposium on Computer Architectures in Vancouver, B.C.

Indeed, the Lx appears to be far closer to hitting the streets than the Pico project ever was.

In terms of design, the basic Lx is laid out as a cluster of four VLIW execution units. That is, the low-end design would be a four-issue machine containing four 32-bit integer ALUs, two 16 x 32 multipliers, one load/store unit and one branch unit.

An eight-issue device could be constructed by ganging togethe r two clusters. The added cluster would bring along its own set of registers, along with other detritus to minimize the difficulties inherent in scaling up a processor.

In their recent paper, the companies' engineers pointed to two specific concepts behind the Lx. "The first was the development of a new, clustered VLIW core architecture and microarchitecture specialized to an application domain [embedded] that ensures scalability and customizability."

The second is the availability of "a tool chain based on aggressive instruction-level parallelism (ILP) compiler technology that gives the user a uniform view of the platform at the programming language level."

The Lx also relies on a two-level code-compression scheme. The instruction cache is compressed so that unused slots don't consume space during encoding, the engineers wrote. More ambitious is an effort in the works to compress binaries with Huffman-like techniques and then decompress blocks of instructions during I-cache refills.

HP devel oped the instruction set architecture as well as much of the software behind the Lx. ST is implementing the hardware.

HP officials could not be reached at press time; however, it's thought that Josh Fisher, an HP engineer who is often referred to as "the father of VLIW," is heavily involved in the HP side of the effort.

"The Lx project," ST's Shepherd said, "has concentrated on producing a highly automated way of exploring architectures — not implementing them, but exploring them."

Though Shepherd's quote sounds cryptic, he meant that the process is not yet entirely hands-off. Right now, the tools output a compiled device description, which must be tweaked. But he sees events moving in the direction of eventual full automation.