DFM Parametric Yield Models for Memory IPs

Most DFM companies only deal with 'cells' or 'gates', but not memory IPs. With patented technologies, Legend’s CharFlo-Memory! can enable the parametric yield models of memory IPs.

SANTA CLARA, Calif., July 13, 2006 – Legend Design Technology, Inc. announced that its CharFlo-Memory! toolset has been extended for the applications of characterizing DFM ‘parametric yield models’ of memory IPs in SoC (system-on-chip) designs. CharFlo-Memory! has been successfully adopted by major foundries, IDMs and fabless design companies for automatic memory IP verification and characterization.

The proactive DFM (design-for-manufacturing) flow consists of yield models and their characterization of the following

1. Random yield models (Defects)
2. Design Systematic yield models (Layout), and
3. Parametric yield models (Electric)

The parametric yield models (Electric) are usually based upon process variations and statistical simulations.

Nowadays, most DFM companies working on parametric yield models deal with only 'cells' or 'gates', but not memory IPs. However, memory IPs have usually taken the majority of chip areas in SoC designs. Therefore, the effects of memory IPs must be addressed.

With patented technologies, Legend’s CharFlo-Memory! shall enable the parametric yield models of memory IPs. For any memory instance from either commercial or in-house memory compilers, CharFlo-Memory! can automatically generate

1. 'Critical-path' circuits, which enables the statistical circuit simulation across process variations by reducing circuit size and simulation time, and
2. 'Critical-yield’ signals, which enables the yield analysis across process variations, e.g. sense-amplifier input vs. noise margin.

The circuit netlist of a layout-extracted memory IP can be enormous. This poses a major bottleneck for statistical simulation across process variations. Therefore, building critical-path circuits becomes necessary. CharFlo-Memory! automatically builds critical-path circuits to reduce the simulation time. Furthermore, an Asymptotic Waveform Evaluation (AWE)-based RC reduction has been built into the CharFlo-Memory!. The critical coupling effects that are necessary for memory simulation are always taken into account.

In memory designs, the most critical 'electric' parameter would be the 'sense-amplifier input voltage', which shall directly impact the yields if less than the noise margin. When it is combined with process variations and statistical modeling, we could get an associated probability distribution related to the parametric yield model. For any memory instance from either commercial or in-house memory compilers, CharFlo-Memory! can accurately characterize the 'sense-amplifier input voltage' at any PVT (process, voltage and temperature) through automatically recognizing those ‘critical-yield’ signals such as sense-amplifier inputs and sensing controls.

"In the DFM flow of variation-aware IC designs, both cell library and memory IPs should be characterized for parametric yield models across process variations." said Dr. You-Pang Wei, president and chief executive officer of Legend Design Technology, Inc. "For cell library, there have already had the EDA tools for statistical timing and extraction results. For memory IPs, Legend’s CharFlo-memory! can be applied for extracting parametric yield models by ‘critical-path’ circuit simulation and ‘critical-yield’ signal analysis. We are fully committed to provide robust DFM solutions that enable the parametric yield models associated with memory IPs in SoC designs."

About Legend

Legend Design Technology Inc. is a leading provider of circuit simulation and semiconductor IP characterization software for SoC designs. With an emphasis on productivity and value, Legend’s CharFlo-Memory! toolset revolutionizes the time-consuming and error-prone processes associated with characterization. MSIM is Legend’s high-accuracy SPICE circuit simulator with great convergence and extensive model support. Turbo-MSIM is Legend’s high-speed and high-capacity circuit simulator ideal for timing and power simulation, and function verification. Both simulators are well designed for nanometer technology challenges, and provide excellent price performance. For more information, visit www.LegendDesign.com.