USB2.0 OTG PHY supporting UTMI+ level 3 interface - 28HK/55LL
Set- top box SoC ready for high-speed demands
Set- top box SoC ready for high-speed demands
By Daniel Eiref, Director of Set-Top Marketing, Consumer Products Group, ATI Technologies Inc., Markham, Ontario, EE Times
December 18, 2001 (1:16 p.m. EST)
URL: http://www.eetimes.com/story/OEG20011218S0051
The European Multimedia Home Platform (MHP) defines a generic interface between interactive digital applications and the computers or set-top-box terminals on which those applications execute. This Java-based interface decouples different providers' applications from the specific hardware and software details of various MHP terminal implementations. It enables digital content providers to address all types of terminals ranging from low-end to high-end set-top boxes, integrated digital TV sets and multimedia PCs. But it will require a great number of graphics Mips to decode. At its heart, MHP is simply a common application programming interface that is completely independent of the hardware platform it is running on. The open-standard MHP platform will alter existing software platforms by combining them into one, upon which it will be possible to author content once and run it anywhere. Enhanced broadcasts, interactive broadcasts and Internet content from different providers can be accessed through a single device such as a set-top box or interactive digital television. MHP is expected to enable a horizontal market for content, applications and services environments over multiple delivery mechanisms (cable, satellite, terrestrial and so on). In the United States, CableLabs, the standards-setting body for cable modems and similar equipment, has adopted MHP as the open standard for cable set-tops in North America. The business implications for linking the broadcasting and Internet worlds are enormous, as exciting new content spreads. According to Cahners In-Stat Group, the total network set-top-box market is estimated to grow from 47 million units in 2000 to 114 million in 2005. At the core of the MHP is a platform known as DVB-J. This includes a virtual machine as defined in the Java Virtual Machine specification from Sun Microsystems Inc. A number of software packages provide generic APIs to a wide range of features of the platform, and MHP applications access the platform only by means of these specified APIs. MHP implementations are required to perform a mapping between the specified APIs and the underlying resources and system software. While the MHP extends the existing digital video broadcast (DVB) standards for broadcast and interactive services in all transmission networks, including satellite, cable, terrestrial and microwave, it will demand an enormous amount of processing power. ATI Technologies recently launched an integrated system-on-chip for set-top boxes and digital TVs that supports the Multimedia Home Platform specification. The chip can be designed into a wide range of devices, including digital cable, satellite, terrestrial and DSL set-top boxes, digital TVs, home media gateways and wireless TV-enabled Web pads. In addition to Europe's MHP, the ATI chip supports a variety of other broadcast, conditional-access and video formats, including the worldwide DVB standard, the U.S. Advanced Television Systems Committee sta ndard and Japan's Broadcast Satellite Digital standard. The ATI Xilleon is built around a 300-MHz, 32-bit MIPS core. It integrates into a single chip the MIPS CPU, graphics, video, audio, PCI, hard-disk-drive controller and USB capabilities. The integration saves space, power and cost. The MIPS architecture, something of a de facto standard in set-top boxes, is supported by a variety of embedded operating systems, including Windows CE, Linux and VxWorks. A 300-MHz clock speed makes a big difference when running MHP applications and executing Java applets in real-time. While processor speeds and memory sizes depend on the size and complexity of resident applications, the cost of an MHP implementation can be heavy even if part of the program code is divided into flash memory or ROM. According to digital TV principals like Sony, Philips and Nokia, an MHP implementation can make use of at least a 200-MHz processor and 32 Mbytes of memory to serve the application.
Related News
- Sigma Designs Launches First Studio-Grade Set Top Box SoC
- NXP To Show The First Fully Integrated 45nm Set Top Box SoC Based On ARM Cortex–A9 Processors
- Opulan Selects ARM High-Speed Physical Interface Solution For Next Generation Network SoC Designs
- EVE's ZeBu Proven High-Speed Verification Solution for IBM PowerPC 405, 440 SoC Designs
- Renesas Technology Develops Automated Device Sizing System for High-Speed Digital/Analog Converters for SoC Use
Breaking News
- Logic Design Solutions launches Gen4 NVMe host IP
- ULYSS1, Microcontroller (MCU) for Automotive market, designed by Cortus is available
- M31 is partnering with Taiwan Cooperative Bank to launch an Employee Stock Ownership Trust to strengthen talent retention
- Sondrel announces CEO transition to lead next phase of growth
- JEDEC Publishes LPDDR5 CAMM2 Connector Performance Standard
Most Popular
- Arm's power play will backfire
- Alphawave Semi Selected for AI Innovation Research Grant from UK Government's Advanced Research + Invention Agency
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
- Weebit Nano continuing to make progress with potential customers and qualifying its technology Moving closer to finalisation of licensing agreements Q1 FY25 Quarterly Activities Report
- PUFsecurity Collaborate with Arm on PSA Certified RoT Component Level 3 Certification for its Crypto Coprocessor to Provide Robust Security Subsystem Essential for the AIoT era
E-mail This Article | Printer-Friendly Page |