AppNet develops Proteus prototyping system

AppNet develops Proteus prototyping system
By Richard Goering, EE Times
July 26, 2000 (12:41 p.m. EST)
URL: http://www.eetimes.com/story/OEG20000726S0013

MOUNTAIN VIEW, Calif. — A new approach to rapid prototyping that is said to rival real-time speeds is quietly under development by AppNet Inc., a design consulting firm established in 1995. AppNet's Proteus system came into public view in July when the company agreed to develop a specialized version for users of MIPS Technologies Inc.'s 32-bit processor cores.

AppNet, which offers services related to emulation and prototyping, is currently focusing all its work around Proteus. While still a customized solution used at beta sites today, the company expects to offer a production-ready, off-the-shelf EDA tool this fall.

Although established companies like Quickturn, Aptix and Ikos currently dominate the emulation and prototyping markets, AppNet believes there's still a huge untapped opportunity. "We estimate that worldwide, the industry probably spends a billion dollars a year on custom prototyping," said Dick Clover, president and chief execu tive officer of AppNet. "We'd like to get a fair fraction of that market."

What's unique about Proteus is its use of a custom-routed "mezzanine" pc-board to represent interconnect between custom logic blocks implemented in FPGAs. Using this method, AppNet claims it can achieve prototyping speeds between 20 and 50 MHz, and build scalable systems that can handle over 10 million gates. With prices starting at $150,000, the company also claims a considerable cost advantage.

Board help

The company's challenge, however, is to provide users with an easy, automated way of creating those mezzanine boards on their own. At present, AppNet routes those boards as a service for each application.

AppNet was launched by Bob Hafflan, a former customer service manager at Quickturn, and Sam Nicolino, a chip designer from Intel. Clover joined the company November 1999. He was previously president of Intel Magnetics, a wholly-owned subsidiary of Intel focused on b ubble memory.

Clover said the 12-person company currently has two beta sites for Proteus, which he declined to name. Thus far, he said, AppNet is focusing on developers of networking chips as its primary customer base.

Compared to other providers of prototyping tools, AppNet offers a "simpler" interconnect scheme, Clover said. "Other companies typically use active switching to route signals from one part of the box to another," he said. "That adds a lot of cost and slows the system down. We have an interconnect device that allows us to have totally passive connections all the way through the system."

Proteus compiles logic into boards that contain eight to 20 Altera or Xilinx FPGAs, as chosen by the user. Recent systems have used Xilinx Virtex 1000 and 2000 devices. One board can accommodate up to three-million gates, and any number of boards can theoretically be hooked together, Clover said. The boards can fit any other components, such as DRAMs, that can be adapted to 503-pin PGA sockets.

I nterconnect is handled by the main mezzanine board, a multilayer board that contains no components — only copper interconnect. The board can handle over 2,000 I/O signals. It piggy-backs on top of the logic board and uses "Gold Dot" connectors made by Packard-Hughes Interconnect. There are smaller mezzanine boards for clock and incremental routing.

Proteus software runs on a PC, and partitions RTL Verilog netlists into multiple FPGAs. Placement and routing is handled with FPGA vendor tools, which are packaged with Proteus software. There's also software for routing the mezzanine boards, but to date, AppNet personnel have been running that software.

Customer hand-off

"It takes some expertise to work with the software, take a customer design, get it partitioned, and get the whole thing synthesized," said Clover. "As we get to the end of the year, though, we'll have a fairly simple way of training the customers to do it themselves. We don't want to have to be tied to every solution."

Clover said it typically takes two to four weeks to get the software partitioned into the FPGAs, and another week or two to design and build the mezzanine boards.

Debugging requires a logic analyzer. AppNet offers an interface with HP 16700 series logic analyzers that allows users to display signal names. Users can also capture logic analyzer traces and convert them to the VCD format read by Verilog debuggers.

In late July, AppNet and MIPS Technologies announced a partnership in which AppNet will create a version of Proteus for the MIPS 32-bit 4Kc core. This will involve some special adapter cards and interconnect features, as well as an ability to drop one or more MIPS 4Ke silicon devices into the FPGA slots of a logic board.

Entry cost for a Proteus system — including an eight-socket logic board, mezzanines, and partitioning software — is around $150,000. That's low enough, Clover contended, for companies to buy multiple copies and distribute some of them to software developers. Proteus will thus be a vehicle for early software development as well as hardware prototyping.