OCP-IP Announces Release of OCP 2.2 Specification
BEAVERTON, Ore.-- January 10, 2007 -- Open Core Protocol International Partnership (OCP-IP) today announced the release of the OCP 2.2 specification. The specification now includes direct support for flexible multi-frequency clocking, support for two-dimensional block burst sequences, new non-blocking (exact) flow control options, more flexible reset behavior, a new security profile to describe the consistent mapping of security-related information, and a new section dedicated to verification.
OCP now includes an optional EnableClk signal that indicates which rising edges of a reference clock are to be considered rising edges of the OCP clock. The addition of this signal allows the system to control the effective clock frequency of the interface dynamically without introducing extra outputs from phase-locked loops, or requiring additional low-skew clock distribution networks when divided frequency clocks are used.
Many SoC applications today implement graphics or video processing subsystems that interact with two-dimensional frame buffers stored in external memory. OCP 2.2 addresses the performance requirements of such subsystems by adding support for two-dimensional block burst sequences. The OCP block burst sequence encodes all of the required information to complete an entire two-dimensional burst to memory in a single request, enabling both higher interface performance and providing memory controllers with the ability to optimize DRAM page accesses to improve memory throughput.
New non-blocking flow control options have been added to facilitate fully synchronous design styles. The new parameters are used to set the relative protocol timing of the MThreadBusy, SDataThreadBusy, and SThreadBusy signals so they signal flow control for the following clock cycle. This enhancement allows OCP to continue to offer its unique, non-blocking, multi-threaded flow control as clock frequencies increase.
A new section of the specification is integrated which is dedicated to verification, and provides compliance, configuration and functional coverage checks for the OCP interface that helps designers create checking solutions in the language and tools of their choice.
OCP-IP believes a standard is only proven through real-world implementations and products. OCP-IP members, companies with world-class SoC design expertise in their own right, have used OCP in numerous SoC designs which have already shipped in many hundreds of million of units. OCP 2.2 utilizes the collective experience of these SoC designers and EDA providers and directly addresses their enhancement recommendations with the new specification.
Work on OCP 2.2 was executed by members of the OCP-IP Specification Working Group including: MIPS Technologies, Inc., Nokia, Sonics Inc., Texas Instruments, Toshiba and other industry leading companies.
“The community’s working groups are extremely active and have done a tremendous job rapidly evolving the specification,” said Ian Mackintosh, president of OCP-IP. “Adoption of OCP has been dramatic and we are excited to see the new features of OCP 2.2 utilized in real world implementations.”
About OCP-IP
The OCP International Partnership Association, Inc. (OCP-IP), formed in 2001, promotes and supports the Open Core Protocol (OCP) as the complete socket standard ensuring rapid creation and integration of interoperable virtual components. OCP-IP's Governing Steering Committee participants include: Nokia (NYSE:NOK), Texas Instruments (NYSE:TXN), Toshiba Semiconductor Group (including Toshiba America TAEC), and Sonics. OCP-IP is a non-profit corporation delivering the first fully supported, openly licensed, core-centric protocol comprehensively fulfilling system-level integration requirements. The OCP facilitates IP core reusability and reduces design time, risk, and manufacturing costs for SoC designs. VSIA endorses the OCP socket, and OCP-IP is affiliated with VSIA. For additional background and membership information, visit www.OCPIP.org.
|
Related News
Breaking News
- Logic Design Solutions launches Gen4 NVMe host IP
- ULYSS1, Microcontroller (MCU) for Automotive market, designed by Cortus is available
- M31 is partnering with Taiwan Cooperative Bank to launch an Employee Stock Ownership Trust to strengthen talent retention
- Sondrel announces CEO transition to lead next phase of growth
- JEDEC Publishes LPDDR5 CAMM2 Connector Performance Standard
Most Popular
- Arm's power play will backfire
- Alphawave Semi Selected for AI Innovation Research Grant from UK Government's Advanced Research + Invention Agency
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
- Weebit Nano continuing to make progress with potential customers and qualifying its technology Moving closer to finalisation of licensing agreements Q1 FY25 Quarterly Activities Report
- PUFsecurity Collaborate with Arm on PSA Certified RoT Component Level 3 Certification for its Crypto Coprocessor to Provide Robust Security Subsystem Essential for the AIoT era
E-mail This Article | Printer-Friendly Page |