VSIA Announces Release of QIP Metric Now Publicly Available with Hard IP Extension
Verification IP Extension Enters Beta Testing
Wakefield, MA—April 9, 2007—The VSI Alliance (VSIA), the leading IP standards body for the electronics industry, today announced the Quality IP (QIP) Metric version 3.0, which includes the hard IP extension, is now publicly available. In addition to the public release of the hard IP extension, VSIA is also announcing that the verification IP extension to the QIP Metric is entering beta testing. Industry leading companies including AMI Semiconductor, Denali Software, edacentrum, Freescale Semiconductor, LSI, Mentor Graphics and Synopsys participated in the development and beta testing of the newest version of the QIP Metric. QIP Metric v3.0 is available for free download from the VSIA website at www.vsi.org.
QIP Version 3.0 includes enhanced support for hard IP quality metrics, including support for different types of hard IP, hierarchical evaluation and graphical results representations, and many automated features that are new to this version. Included in this release is the verification IP extension which includes Quality metrics for drivers and responders, monitors, bus functional models and stimuli generators.
Originally released to the public in January 2006 as a standardized platform for evaluating IP Quality the QIP Metric and has seen over 1000 downloads. This latest release with the automated features and hard IP extension integrated with the previously released vendor assessment metrics and soft IP extensions, the QIP Metric continues to develop as a complete IP Quality tool for the entire design chain— from vendors to integrators to foundries.
“The VSIA continues to enhance the QIP Metric in order to address the varied and growing needs of the industry. The VSIA QIP has become a widely adopted standard improving overall efficiency of exchanging and integrating Semiconductor IP (SIP) cores, we encourage our suppliers to provide data in this format to simplify their qualification work.” said Gary Delp, CTO of VSIA and Distinguished Engineer of LSI.
QIP Roadmap
Following the beta testing period for the verification IP extension, the VSIA IP Quality workgroup is targeting a mid-2007 public release. VSIA is currently seeking participation for the software IP workgroup from the industry. If you are interested in joining, contact Jodi Bova at membershipservices@vsi.org.
QIP Metric Logos
Companies can promote their QIP Metric status through the use of the VSIA QIP Metric logos. These logos are graphic symbols identifying IP Vendors that have gone through vendor qualification (QIP Metric Rated logo) or IP Integrators that require QIP Metric scores from their vendors (QIP Metric Adopter logo). QIP Metric logos are available for free download from the VSIA website at http://vsi.org/pillars/quidelines.htm
About VSIA
The VSI Alliance (VSIA) is an open, international organization that includes representatives from all segments of the SoC industry: system houses, semiconductor vendors, Electronic Design Automation (EDA) companies, and Intellectual Property (IP) providers. VSIA’s mission is to dramatically enhance the productivity of the SoC design community by providing leading-edge commercial and technical solutions and insight into the development, integration and reuse of IP. VSIA has wide industry participation from companies around the world. Membership is open to any company with an interest in the development and promotion of business solutions and open standards used in the design of Systems-on-Chip. For more information, visit the VSIA web site at www.vsi.org, or e-mail to info@vsi.org.
|
Related News
- Hard IP Extension of the VSIA QIP Metric Enters Beta Testing
- VSIA QIP Metric Completes Beta Program QIP Metric now available to public
- VSIA Quality IP Metric Now Includes Verification IP Extension
- VSIA Works with Hong Kong to Extend QIP Metric
- VSIA Publicly Releases Updated Hard and Soft IP Tagging Standards; Freescale donates tag reader/writer to VSIA
Breaking News
- Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7M
- TSMC drives A16, 3D process technology
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
E-mail This Article | Printer-Friendly Page |