Verification hardware to stage a comeback at DAC

Verification hardware to stage a comeback at DAC
By Richard Goering and Michael Santarini, EE Times
May 30, 2000 (12:28 p.m. EST)
URL: http://www.eetimes.com/story/OEG20000530S0015

LOS ANGELES — With five major announcements in queue for next week's Design Automation Conference (DAC), it's clear hardware-assisted verification is making a stunning resurgence. Tharas Systems and Aldec are debuting in this market, while Quickturn, Aptix and Simutech are rolling out new types of products and services.

Functional verification tools based on specialized hardware have been a hard sell, especially as workstations have fallen in price and surged in performance. But now, the verification demands of large system-on-chip designs are spawning new tools and approaches.

Traditionally, hardware-assisted verification has comprised two markets: acceleration, in which specialized hardware speeds an existing gate-level simulator; and emulation, in which gate-level netlists are mapped into FPGAs or custom processors. But the new products, which are mostly aimed at register-transfer-level (RTL) verification, don't fit so cleanly into these previously defined categories.

"The whole emulation and acceleration category took off last year," said Gary Smith, chief EDA analyst at research house Dataquest Inc. (San Jose, Calif.). "It looks like big growth. I may be doubling the 1999 [revenue] number and the growth estimates."

Smith said that Tharas Systems Inc. (Santa Clara, Calif.), a startup making its first public appearance at DAC, is attracting a lot of attention with its RTL accelerator. So is Aptix Corp. (San Jose), which is beefing up its rapid prototyping tools. Smith also said that the Quickturn-Simutech announcement, in which Quickturn is using Simutech technology to enter the rapid-prototyping market, should go over well.

Another company that's claiming success in the hardware-assisted market is newcomer Axis Systems (Sunnyvale, Calif.), which last month unveiled SEmulation, a hardware-as sisted product intended to combine the best of both simulation and emulation. That product will have its first public showing at next week's conference here.

Tharas Systems believes it has a new approach to hardware-assisted verification as well. The company's Hammer 50/32 is an RTL accelerator that uses a completely different architectural approach from previous products, one that stems from the founders' experience as chip designers at a networking startup called ZeitNet. "We had a clean slate to use a massively parallel solution based on an ASIC," said Steve Carlson, Tharas' chief executive officer. "It allows you to have very fast compile times, full signal visibility, support for debugging and memory modeling, and compatibility with the existing environment."

Verilog remains

According to Tharas, a key advantage of Hammer 50/32 is that designers can continue using their Verilog simulation, testbench generation and debugging en vironments. The product currently accelerates Synopsys Inc.'s VCS Verilog simulator, with support for Cadence Design Systems Inc.'s NC-Verilog coming in July. It takes gate-level, RTL and even some behavioral Verilog code, and can run in standalone mode or in cosimulation with the Verilog software simulator.

Physically, the Hammer 50/32 consists of eight processor boards, each with 128 processors, housed in a CompactPCI chassis. It's able to handle up to 8 million RTL gates, and provides 1 Gbyte of memory for memory modeling. The Hammer 50/32 uses what Carlson called "a big memory-mapped architecture," with interconnect handled by ASICs instead of more expensive FPGA-based solutions.

Performance ranges from 10,000 to 100,000 cycles/second, depending on how much parallelism is in the design. The speed also depends on the testbench; Carlson said that a testbench written in Verisity's "e" language will slow the run-times. Tharas resells Novas debugging software, and debugging can also be provided by any third-party product that accepts Verilog VCD files.

The Hammer 50/32 is shipping now starting at $200,000. Tharas has so far named two customers for the tool — Tensilica and Lexra.

Another newcomer to hardware-assisted verification is Aldec Inc. (Henderson, Nev.). This longtime provider of FPGA design tools is stepping up to high-end ASIC design with Active-HDL/DL, a dual-language simulator, and Hardware Embedded Simulation (HES), a gate and RTL acceleration system for VHDL and Verilog.

Stanley Hyduke, Aldec's president and chief executive officer, described HES as an "incremental system-level breadboarding platform" consisting of three parts: the Active-HDL/DL software simulator; RTL acceleration boards; and gate-level acceleration boards. All are synchronized on an event-by-event basis, allowing users to download chunks of code that don't need extensive interactive debugging of the hardware boards.

Those accelerator boards will fit directly into th e PCI slot of a host PC or Unix workstation. Aldec plans to support Windows NT first, followed by Linux and then by Unix.

Taking on ModelSim

Active-HDL/DL is Aldec's challenge to the popular dual-language ModelSim simulator from Model Technology, with an interesting twist: support for EDIF simulation as well as VHDL and Verilog. David Rinehart, vice president of marketing at Aldec, said EDIF simulation is very helpful for legacy intellectual property (IP) created with schematic tools.

The RTL boards, which won't be available until the first quarter of 2001, will contain 64 interconnected processors. RTL code will be synthesized into what Hyduke called a "C-like language." Compilers are under development by Prus, an Aldec sister company.

Both the RTL and the gate-level boards will provide up to 8 million-gate capacity. It's not yet known whether the RTL boards' interconnected processors will be implemented using ASICs or FPGAs. Users of RTL boards, but not the gate-level boards, wil l have all the debugging features of Active-HDL/DL.

The gate-level boards, scheduled to ship in August, use Xilinx Inc. Virtex FPGAs, which are configured using incremental synthesis software from Alatek, another Aldec sister company. Users can input one netlist per FPGA. Hyduke said gate-level speeds are 50 to 100 times faster than RTL software simulation.

The Active-HDL/DL simulator will be available in June starting at $9,800. The full HES system starts at $65,000.

Simutech Corp. (Vancouver, Wash.) made its debut at last year's DAC with Rave, a new type of system-on-chip (SoC) verification system. At this year's DAC, Rave will show up in two places: as part of Simutech's eValab platform for rapid IP evaluation, and as the basis for Quickturn's Rapid Prototyping System.

IP evaluation

Rave consists of a cabinet filled with CoreBoards, each of which models one IP block using a high-density FPGA or bonded-out core. It can be used standalone or with a host HDL simulator. This Java-based product can be remotely accessed over the Internet, a feature that Simutech is leveraging for its eValab Platform.

The idea of eValab, said Steve Glaser, vice president of marketing at Simutech, is to help geographically dispersed groups quickly evaluate internal or external IP using an intranet or the Internet. "Users are looking for assessments of quality, functionality and systems performance," said Glaser. "What's really critical is evaluation in a systems context."

At the heart of eValab is the eValab Server, which is essentially Rave with some additional software. Support has been added for rapid design-context switching, job routing and queueing, and a batch-mode command interface is available for multiuser sessions. The licensing model allows for a large number of users, but with limited session times aimed at evaluation, not verification.

A "Webware" library provides applets and utilities to support two levels of evaluation. The first uses a n interactive data sheet, called iDatasheet, for a very fast top-level evaluation. The second uses iLab, which allows the user to bring in testbenches, run a host simulation and dump a Verilog VCD file to a waveform viewer. A free iLab Client must be downloaded to support this level of evaluation.

The eValab Platform is set for production shipments in the third quarter, with prices starting at $135,000 for a two-CoreBoard configuration. Glaser said that Simutech will focus on selling eValab, while Quickturn, with its much larger sales force, will be Simutech's outlet for verification products.

For its part, Quickturn, now a division of Cadence Design Systems (San Jose), is coming to DAC with its own value-added version of Rave. The Rapid Prototyping System (RPS) adds Quickturn partitioning and synthesis software options, along with various hardware interface options and a connection to the new Mercury Plus emulation system.

George Zafiropoulos, vice preside nt of marketing for Quickturn, said the RPS will be used after verification and in-circuit emulation to create a rapid SoC hardware prototype that can be pushed over to the software engineers.

The RPS essentially allows users to add standard parts, bonded-out cores, RAM, analog, interface and custom logic embedded in FPGAs to the Simutech-designed CoreBoards. Customers enter RTL custom logic and do partitioning using an OEM version of Synplicity's Synplify FPGA synthesis tool and its Certify autopartitioning tool.

Once the system prototype has been configured with the RPS, users can, with the assistance of Quickturn, create several so-called "SoC replicants" for software developers. These consist of essentially the same chassis but without the system developer software. The SoC replicants can then be rolled over to the software developers.

RPS systems with one CoreBoard start at $315,000. Replicants start at $170,000. Products will be available in the third quarter.

Mercury rising

Meanwhile, Quickturn claims that its new Mercury Plus system boasts vastly improved compile time, capacity and debug features over the original Mercury emulation system. Where Mercury used off-the-shelf FPGAs (Xilinx 4036 devices), the Plus system uses custom FPGAs designed by Cadence specifically for its emulation system.

The result, according to Zafiropoulos, has been a new Mercury emulator that can handle up to 20 million ASIC gates and up to 2 Gbytes of memory, compile roughly five times faster than the original Mercury box and allow two to three bug fixes a day, rather than one.

Zafiropoulos said the greatest benefit of using the custom FPGAs has been shorter compile times. Also, he said, these devices have allowed Quickturn to offer fast yet accurate asynchronous modeling. In the past, he said, emulators have either used a slow but accurate approach, or have resynthesized asynchronous logic into synchronous logic for better run-times.

The Mercury Plus starts at $595,000 for a million-g ate configuration. It will ship in July. Quickturn is also bringing a high-speed Ethernet verification environment, based on Cobalt and Mercury emulation systems, to DAC.

In the rapid-prototyping market, Quickturn will bump up against Aptix. That company has DAC announcements of its own — namely, an Internet-enabled verification service and new modules that double the capacity of its MP4FC and MP3FC emulation systems, which now can handle 3.6 million and 2.7 million gates, respectively.

Ralph Zak, vice president of marketing for Aptix, said the new eSoCVerify.com virtual private network allows Aptix to take on one of the most time-consuming tasks for customers: programming the Aptix emulators. The intent is to give customers more breathing space to concentrate on their designs.

Zak said Aptix has set up a secure server system for its eSoCVerify.com site. Customers can send in IP blocks they need verified, or have Aptix program custom blocks or entire designs into the customer' s Aptix system based on RTL code that the customer submits. If the customer already owns an emulator, Aptix can ship flash modules containing the design, which can be plugged into the customer's emulator. Because Aptix systems are Ethernet enabled, Aptix can also download bit streams to the customer's emulation box.

Zak said a typical engagement for eSoCVerify.com will run in the $50,000 to $150,000 range.

In addition, Aptix said, it has increased the capacity of its MP4FC and MP3FC emulation systems. The gain, according to Zak, largely comes from the use of two Xilinx V2000E FPGAs on each emulation module rather than one.

"We have doubled the density of each module, so now each module handles roughly 450,000 ASIC gates," said Zak. "Customers can add eight of our new modules to their MP4FC to get a 3.6 million-gate capacity, plus 10 Mbits of block memory." Adding six modules, he said, yields a capacity of 2.7 million ASIC gates and 7 Mbits of block memory.

Zak said customers can link two Aptix emulation systems to get a 5 million to 6 million ASIC gate capacity or more through Aptix design services. For most designs, he said, emulation speed is not really affected by the additional gates, but data path-intensive designs will see some slowdown.

The MP4FC is priced at $345,000 with eight modules and $280,000 with six. The double-density modules are $22,000 apiece.