English
ARC readies energy saving cores
John Walko, EE Times
(12/05/2007 10:23 AM EST)
SANTA CLARA, Calif --- ARC International is readying a range of cores, dubbed Energy PRO, that adds active power management capability to its line-up of IP cores. The cores come validated with Cadence Low Power Solution and Common Power Format (CPF) through a partnership between the ARC, Cadence and Virage.
Full details of the cores are due to be revealed later this month but at briefings ahead of ARC's ConfigCon held here, the company said the integrated hardware/software technology and associated design methodology can provide up to four times or more reduction in energy reduction.
Focused on portable applications Energy PRO works with ARChitect, ARC's processor configuration tool, to capture the power design intent of a custom configured ARC processor cores. Then tight coupling with the Cadence Encounter IC Design Platform and low-power logic libraries from ARC partners support a designer's power intent throughout the entire SoC design flow.
The company said a version for the UPF flow is in the works, but would not specify when that would be available.
The key hardware elements implemented include straight-forward clock gating, power shutdown modes, and dynamic voltage and frequency scaling techniques.
(12/05/2007 10:23 AM EST)
SANTA CLARA, Calif --- ARC International is readying a range of cores, dubbed Energy PRO, that adds active power management capability to its line-up of IP cores. The cores come validated with Cadence Low Power Solution and Common Power Format (CPF) through a partnership between the ARC, Cadence and Virage.
Full details of the cores are due to be revealed later this month but at briefings ahead of ARC's ConfigCon held here, the company said the integrated hardware/software technology and associated design methodology can provide up to four times or more reduction in energy reduction.
Focused on portable applications Energy PRO works with ARChitect, ARC's processor configuration tool, to capture the power design intent of a custom configured ARC processor cores. Then tight coupling with the Cadence Encounter IC Design Platform and low-power logic libraries from ARC partners support a designer's power intent throughout the entire SoC design flow.
The company said a version for the UPF flow is in the works, but would not specify when that would be available.
The key hardware elements implemented include straight-forward clock gating, power shutdown modes, and dynamic voltage and frequency scaling techniques.
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