LSI Logic, NEC adopt MoSys 1T-SRAM technology

Hitoshi Yoshizawa, chief manager of NEC's communications system LSI departme nt, said that exploding system bandwidth requirements for wired communications devices like hubs and routers are driving strong demand for both fast on-chip bandwidth and chip-to-chip interfaces. "We need bigger on-chip memory so more of the packet data can get stored in the chip, so that we can get better bandwidth," he said.

On that score, the MoSys solution could provide a good compromise between a large, standard six-transistor SRAM cell and a dense but expensive embedded DRAM, he said. The 1T-SRAM cell takes up a third of the area of a six-transistor SRAM cell, though it is three times larger than a standard embedded DRAM, observers said.

"With MoSys, high-speed random access can be implemented in either an embedded-DRAM process or a pure CMOS process if we change the bit cell," Yoshizawa said.

LSI Logic, which is placing more emphasis on communications applications, has already licensed the MoSys memory cell. The company is now evaluating the technology, and plans to first offer it as par t of its 0.18-micron G-12 process, said King Ou, ASIC marketing manager for LSI Logic.

Like NEC, LSI Logic sees a need for higher-density RAM in certain communications chips. "A growing demand for the communication market is the integration of CoreWare library elements with multimegabits of high-performance memories in a single silicon process," said Jordan Plofsky, vice president and general manager of LSI Logic's networking product division. "MoSys' 1T-SRAM provides a solution for that multi-megabit memory integration."

Though NEC has not finalized a licensing agreement with MoSys, it is considering using a pure CMOS process to integrate that company's 1T-SRAM cell into wired-network communications ICs. While standard embedded DRAM has better density than the 1T-SRAM cell because the structure of the cell capacitor is built vertically, it requires extra mask steps to build the stacked layers or dig the capacitor into a trench cell. And more mask layers mean yields suffer, causing manufacturing co sts to rise, Yoshizawa said.

A standard embedded-DRAM approach is fine for high-volume applications like game machines, where costs can be amortized over several years. But it's much harder to justify in applications like routers and switches, which are more customer-specific and don't enjoy such large volumes, Yoshizawa said.

That's why NEC is not offering a standard embedded DRAM for customers in that area.

The MoSys cell looks like a DRAM with one transistor and one capacitor, but the difference is that the capacitor is flattened. By making the capacitor more planar, Yoshizawa said, chip manufacturers don't need the extra processing steps required for more-vertical capacitor structures.

The MoSys 1T-SRAM is about three times larger than a standard embedded-DRAM cell. But when compared with a standard six-transistor SRAM cell now in wide use among ASIC suppliers, the cell size is one-third the area, MoSys said.

So far, NEC is considering adding the MoSys cell to its 0.18-micron library . However, the company is unsure whether 1T-SRAM can scale down to smaller line widths, and so it will hold off adopting it for its 0.13-micron process technology. Instead NEC will provide customers its internally developed four-transistor SRAM cell.

Mark-Eric Jones, vice president and general manager of intellectual property for MoSys, said the company is confident that the technology can scale. Test chips based on 0.15-micron design rules have taped out, and several companies have already licensed the memory cell for 0.13-micron designs, he said.

"We expect 1T-SRAM to scale even better than either 4T- or 6T-SRAM," he said. "Our multibank architecture allows us to compensate for lower cell capacitance values while maintaining the same or better signal-to-noise levels and performance in memory."

LSI, for its part, believes the 1T-SRAM cell is suitable for more-advanced process technologies. Assuming the evaluation is successful, LSI Logic will move to also offer 1T-SRAM in its forthcoming 130-nan ometer (O.13-micron) process technology and possibly in its 0.25-micron process, Ou said.

In the middle of the year LSI Logic is due to reach full production on a 130-nm process that delivers up to 12 million usable logic gates running at up to 650-MHz clock frequency.

"We don't have a specific time for when we'll be able to use the [1T-SRAM] technology in ASSPs or offer it to ASIC customers," Ou said.

Like NEC, LSI Logic is not offering embedded DRAM in its ASIC libraries because of cost and performance reasons.