English
nSys Offers World's Largest Portfolio of Verification IPs for OVM-Based SystemVerilog Environments
Available for Mentor Graphics Questa Verification Platform
NEWARK, CA -- February 19, 2008 -- nSys Design Systems, the developer of the world's largest portfolio of Verification IPs, announced today the availability of nSys' Verification IP products integrated with the Open Verification Methodology (OVM) environment. The nSys Verification IPs for OVM-based environments are available for standard interfaces such as AMBA AXI, Ethernet, PCIe, SATA, and USB etc.
"We have seen rapid acceptance of SystemVerilog in the last few months," said Atul Bhatia, CEO of nSys Design Systems. "The availability of commercial verification tools from nSys and Mentor Graphics will help mutual customers leverage the full potential of SystemVerilog and OVM to develop verification environments that before were only a dream."
The demand by users for verification data portability and verification platform interoperability has driven the verification community to OVM. Being a member of Mentor Graphics Questa Vanguard program, nSys is able to qualify its Verification IP with the Questa verification platform and offer early support for OVM. As a recognized OVM Partner, nSys can leverage electronic design automation industry collaboration in the development and support of OVM as well as provide early feedback and rapid support of OVM.
"We worked closely with nSys upon the release of OVM so our mutual customers could use the nSys Verification IPs within the Questa verification environment," said Dennis Brophy, Director of Strategic Business Development of Mentor Graphics Design Verification and Test division. "The availability of nSys Verification IPs for OVM-based environments will enable designers to rapidly adopt OVM and drastically reduce the verification effort of complex designs."
Pricing and Availability: OVM-based Verification IPs are available today for a wide variety of protocols. Pricing starts at $5,000 for one Annual encrypted license.
About nSys: nSys leverages the world's largest portfolio of Verification IPs it has developed, to provide products & services to Accelerate Designs of its customers developing ASIC or FPGA. The nVS family has proven VIPs for standard interfaces such as PCI Express, Ethernet, SATA, SAS, AXI, USB, SDIO, DDR3, DDR2 etc. For more information, please visit www.nsysinc.com
NEWARK, CA -- February 19, 2008 -- nSys Design Systems, the developer of the world's largest portfolio of Verification IPs, announced today the availability of nSys' Verification IP products integrated with the Open Verification Methodology (OVM) environment. The nSys Verification IPs for OVM-based environments are available for standard interfaces such as AMBA AXI, Ethernet, PCIe, SATA, and USB etc.
"We have seen rapid acceptance of SystemVerilog in the last few months," said Atul Bhatia, CEO of nSys Design Systems. "The availability of commercial verification tools from nSys and Mentor Graphics will help mutual customers leverage the full potential of SystemVerilog and OVM to develop verification environments that before were only a dream."
The demand by users for verification data portability and verification platform interoperability has driven the verification community to OVM. Being a member of Mentor Graphics Questa Vanguard program, nSys is able to qualify its Verification IP with the Questa verification platform and offer early support for OVM. As a recognized OVM Partner, nSys can leverage electronic design automation industry collaboration in the development and support of OVM as well as provide early feedback and rapid support of OVM.
"We worked closely with nSys upon the release of OVM so our mutual customers could use the nSys Verification IPs within the Questa verification environment," said Dennis Brophy, Director of Strategic Business Development of Mentor Graphics Design Verification and Test division. "The availability of nSys Verification IPs for OVM-based environments will enable designers to rapidly adopt OVM and drastically reduce the verification effort of complex designs."
Pricing and Availability: OVM-based Verification IPs are available today for a wide variety of protocols. Pricing starts at $5,000 for one Annual encrypted license.
About nSys: nSys leverages the world's largest portfolio of Verification IPs it has developed, to provide products & services to Accelerate Designs of its customers developing ASIC or FPGA. The nVS family has proven VIPs for standard interfaces such as PCI Express, Ethernet, SATA, SAS, AXI, USB, SDIO, DDR3, DDR2 etc. For more information, please visit www.nsysinc.com
|
||||||
Related News
- Introducing the largest portfolio of Verification IP Cores for all types of Testbench verifications of different protocols and interfaces for your advanced Design IPs which are now available for immediate licensing
- TSMC 12FFC silicon proven SERDES Phy IPs' for HDMI 2.1, PCIe Gen5, DDR4, USB 4 & MIPI Interfaces available immediately for your next SoC
- SmartDV's AMBA Verification IPs Deployed Worldwide by KYOCERA Document Solutions
- PLDA's XpressRICH3-AXI PCI Express 3.0 IP with AMBA AXI Support Passes PCI-SIG PCIe 3.0 Compliance Testing
- PLDA Announces Integration of its PCIe 2.0 controller with advanced AMBA AXI interface in Microsemi's new SmartFusion2 SoC FPGA
Breaking News
- Frontgrade Gaisler Unveils GR716B, a New Standard in Space-Grade Microcontrollers
- Blueshift Memory launches BlueFive processor, accelerating computation by up to 50 times and saving up to 65% energy
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Cadence Unveils Arm-Based System Chiplet
Most Popular
- Cadence Unveils Arm-Based System Chiplet
- CXL Fabless Startup Panmnesia Secures Over $60M in Series A Funding, Aiming to Lead the CXL Switch Silicon Chip and CXL IP
- Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
- Eliyan Ports Industry's Highest Performing PHY to Samsung Foundry SF4X Process Node, Achieving up to 40 Gbps Bandwidth at Unprecedented Power Levels with UCIe-Compliant Chiplet Interconnect Technology
- Arteris Selected by GigaDevice for Development in Next-Generation Automotive SoC With Enhanced FuSa Standards
|
E-mail This Article | 
|
|
Printer-Friendly Page |