STMicroelectronics Announces Certified Design Flow to Accelerate Creation of Next-Generation Silicon
Digital and mixed-signal design flows demonstrate significant productivity gains through multiple projects taped out with an advanced electronic system level (ESL) flow
GENEVA, June 9, 2008 -- STMicroelectronics (NYSE: STM), a global leader in providing semiconductor solutions across the spectrum of microelectronics applications, today announced the deployment of a certified electronic system level (ESL) System-on-Chip reference design flow.
The design flow has been adopted and internally distributed following successful tape-outs of more than a dozen ASIC (application specific integrated circuit) designs with productivity gains from four to ten times faster than with traditional methods. Additionally, ST is also meeting increasing demands from industry leaders in consumer markets for complete system-level design platforms integrating digital and RF/mixed-signal technologies. A number of leading-edge ST products have been developed using this reference design flow, such as a 2-megapixel YUV CMOS image sensor and a highly-integrated image processing hardware accelerator for mobile phones.
Aimed at complex designs for next-generation consumer electronics equipment, ST's integrated ESL reference-design flow for complex digital CMOS designs combines high-level synthesis, sequential equivalence checking, power exploration and lint checkers that look for errors in code construction, thereby providing a complete methodology from ANSI C++ to RTL including certified integration ST's certified RTL-to-GDS2 design flow. As a result, hardware designers using ST's ESL reference flow are able to create and verify chips faster, with higher quality.
The advanced design flow is the result of more than three years of close collaboration with best-in-class EDA providers for each of the core ESL technologies. The ST design flow is integrated with Atrenta's industry-standard SpyGlass(R) for RTL lint checking and power analysis; the Mentor Graphics(R) Catapult(R) C Synthesis tool; and Calypto Design Systems' SLEC equivalence checker, providing highly efficient synthesis from pure ANSI C++ to RTL and formally verifying that the resulting RTL implementation is functionally correct. This advanced flow provides a comprehensive solution that includes: RTL lint sign-off; power estimation and exploration; C-to-C formal equivalence checking; C-to-RTL formal equivalence checking; SystemC model generation; and C-to-RTL high-level synthesis, thereby minimizing risk and shortening design cycles with 'real-world' productivity gains of between four and ten times.
Additionally, ST is successfully using its design and verification flow for RF/mixed-signal ICs to accelerate the development of sophisticated mixed-signal chipsets used in multi-band, multi-format wireless products. The RF/mixed-signal design flow is based on Agilent Technologies' Advanced Design System (ADS) software and Mentor Graphics' Catapult C synthesis technology.
Optimized ANSI-C code, which describes the digital element of the chip, is used in Agilent's ADS platform to verify the RF/mixed-signal design performance against published wireless standards. Once verified, this same optimized ANSI-C is then input into Mentor's Catapult C compiler to create very high-speed integrated circuit hardware description language (VHDL) that is used for gate-level synthesis into an ASIC.
"ST has developed one of the industry's most advanced system level design flows to manage the increasing complexity of today's System-on-Chip designs," said Philippe Magarshack, Vice-President and General Manager of Central CAD and Design Solutions at STMicroelectronics. "By integrating best-in-class tool technologies from Agilent, Atrenta, Calypto and Mentor with ST's own design expertise, our system-level design flows can build chips faster, with higher quality and productivity, allowing our customers to derive the maximum benefit from ST's advanced chip technologies."
STMicroelectronics Solution Showcased at DAC 2008
The STMicroelectronics certified ESL reference design flow will be featured at the Mentor Graphics booth at DAC 2008, June 9-12 at the Anaheim (CA) Convention Center. ST is also presenting on the Industrial Usage of ESL synthesis at the HLS Workshop: Back to the Future in Room 208A on June 8, 2008 at DAC.
For further information on the specific CAD tools:
- Agilent's Advanced Design System
- Atrenta's SpyGlass
- Calypto's SLEC equivalence checker
- Mentor's Catapult C
About STMicroelectronics
STMicroelectronics is a global leader in developing and delivering semiconductor solutions across the spectrum of microelectronics applications. An unrivalled combination of silicon and system expertise, manufacturing strength, Intellectual Property (IP) portfolio and strategic partners positions the Company at the forefront of System-on-Chip (SoC) technology and its products play a key role in enabling today's convergence markets. The Company's shares are traded on the New York Stock Exchange, on Euronext Paris and on the Milan Stock Exchange. In 2007, the Company's net revenues were $10 billion. Further information on ST can be found at http://www.st.com.
|
Related News
- Cadence Unveils Next-Generation Palladium Z2 and Protium X2 Systems to Dramatically Accelerate Pre Silicon Hardware Debug and Software Validation
- Rambus Announces Industry-First HBM4 Controller IP to Accelerate Next-Generation AI Workloads
- Siemens delivers end-to-end silicon quality assurance for next-generation IC designs with new Solido IP Validation Suite
- M31 Launches PCI-SIG Certified PCIe 5.0 PHY IP, Partnering with SSD Storage Chipmaker InnoGrit to Advance the Next-Generation PCIe 5.0
- Cadence and UMC Certified mmWave Reference Flow Delivers First-Pass Silicon Success
Breaking News
- Logic Design Solutions launches Gen4 NVMe host IP
- ULYSS1, Microcontroller (MCU) for Automotive market, designed by Cortus is available
- M31 is partnering with Taiwan Cooperative Bank to launch an Employee Stock Ownership Trust to strengthen talent retention
- Sondrel announces CEO transition to lead next phase of growth
- JEDEC Publishes LPDDR5 CAMM2 Connector Performance Standard
Most Popular
- Arm's power play will backfire
- Alphawave Semi Selected for AI Innovation Research Grant from UK Government's Advanced Research + Invention Agency
- Secure-IC obtains the first worldwide CAVP Certification of Post-Quantum Cryptography algorithms, tested by SERMA Safety & Security
- Weebit Nano continuing to make progress with potential customers and qualifying its technology Moving closer to finalisation of licensing agreements Q1 FY25 Quarterly Activities Report
- PUFsecurity Collaborate with Arm on PSA Certified RoT Component Level 3 Certification for its Crypto Coprocessor to Provide Robust Security Subsystem Essential for the AIoT era
E-mail This Article | Printer-Friendly Page |