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DFI Technical Group Releases Low Power Features with New DDR PHY Interface Specification Version 2.1
DFI Specification Available at the New Community Website Aimed At Growing DFI Ecosystem
SUNNYVALE, Calif. -- Oct. 27, 2008 -- Denali Software, Inc., today, as one of the DDR PHY Interface (DFI) specification participating members, announced the availability of the preliminary version of the DFI specification 2.1. The DFI specification extends support to the latest LPDDR2 memory technology and enables new features including frequency change support and low-power PHY options. The collaborative technical working group includes representatives from ARM, Denali, Intel, LSI, Samsung, and STMicroelectronics. This technical group is enhancing the specification with several low-power features aimed at speeding LPDDR memory system design and integration, and reducing verification costs. The preliminary DFI specification 2.1, now available, is just one of the many resources found on the growing DFI ecosystem community website. The website highlights leading DDR DRAM IP and service providers and discusses the upcoming DFI Forum keynote address by Bryan Jones from Intel on Tuesday, October 28 at the Academy Hills in Tokyo, Japan.
"As the migration to LPDDR2 memory and low power continues, there is a need to meet the demand for higher density, speed and lower power," said John MacLaren, chair of DFI Technical Committee and senior staff engineer at Denali. "The latest DFI features will be well suited for low power and embedded system designs which target applications such as cell phones, ultra-mobile PCs and consumer applications."
The DFI specification 2.1 enables a new low-power PHY interface that enables the controller to provide information to the PHY about the state of the system. This feature allows the PHY to take advantage of "down-time" by disabling various power consuming features of the PHY, as appropriate, for the state of the system. The new frequency change feature enables the controller to inform the PHY when a frequency change will occur and simplifies the frequency change process and the integration of devices that support this functionality.
"There is a rapid rate of adoption of this specification throughout the industry with over 3,000 downloads of the specification to date," Bryan Jones, Corporate External IP Management, Mobility Group for Intel Corporation said. "I am looking forward to focusing on continued expansion of the ecosystem as well as on the DDR4 specification next year."
About the DFI Specification
The DDR PHY Interface (DFI) specification defines an interface protocol between memory controller logic and PHY interfaces, with a goal of reducing integration costs while enabling performance and data throughput efficiency. The protocol defines the signals, timing, and functionality required for efficient communication across the interface. The specification is designed to be used by developers of both memory controllers and PHY designs, but does not place any restrictions on the how the memory controller interfaces to the system design, or how the PHY interfaces to the DRAM devices. For more information about the DFI specification, its community, activities and how to participate, visit: http://www.ddr-phy.org.
About Denali Software
Denali Software, Inc. is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry's most trusted solutions and platforms for deploying PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali's EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Sunnyvale, California and has offices around the world to serve the global electronics industry. More information about Denali, its products, and services is available at http://www.denali.com.
SUNNYVALE, Calif. -- Oct. 27, 2008 -- Denali Software, Inc., today, as one of the DDR PHY Interface (DFI) specification participating members, announced the availability of the preliminary version of the DFI specification 2.1. The DFI specification extends support to the latest LPDDR2 memory technology and enables new features including frequency change support and low-power PHY options. The collaborative technical working group includes representatives from ARM, Denali, Intel, LSI, Samsung, and STMicroelectronics. This technical group is enhancing the specification with several low-power features aimed at speeding LPDDR memory system design and integration, and reducing verification costs. The preliminary DFI specification 2.1, now available, is just one of the many resources found on the growing DFI ecosystem community website. The website highlights leading DDR DRAM IP and service providers and discusses the upcoming DFI Forum keynote address by Bryan Jones from Intel on Tuesday, October 28 at the Academy Hills in Tokyo, Japan.
"As the migration to LPDDR2 memory and low power continues, there is a need to meet the demand for higher density, speed and lower power," said John MacLaren, chair of DFI Technical Committee and senior staff engineer at Denali. "The latest DFI features will be well suited for low power and embedded system designs which target applications such as cell phones, ultra-mobile PCs and consumer applications."
The DFI specification 2.1 enables a new low-power PHY interface that enables the controller to provide information to the PHY about the state of the system. This feature allows the PHY to take advantage of "down-time" by disabling various power consuming features of the PHY, as appropriate, for the state of the system. The new frequency change feature enables the controller to inform the PHY when a frequency change will occur and simplifies the frequency change process and the integration of devices that support this functionality.
"There is a rapid rate of adoption of this specification throughout the industry with over 3,000 downloads of the specification to date," Bryan Jones, Corporate External IP Management, Mobility Group for Intel Corporation said. "I am looking forward to focusing on continued expansion of the ecosystem as well as on the DDR4 specification next year."
About the DFI Specification
The DDR PHY Interface (DFI) specification defines an interface protocol between memory controller logic and PHY interfaces, with a goal of reducing integration costs while enabling performance and data throughput efficiency. The protocol defines the signals, timing, and functionality required for efficient communication across the interface. The specification is designed to be used by developers of both memory controllers and PHY designs, but does not place any restrictions on the how the memory controller interfaces to the system design, or how the PHY interfaces to the DRAM devices. For more information about the DFI specification, its community, activities and how to participate, visit: http://www.ddr-phy.org.
About Denali Software
Denali Software, Inc. is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry's most trusted solutions and platforms for deploying PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali's EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Sunnyvale, California and has offices around the world to serve the global electronics industry. More information about Denali, its products, and services is available at http://www.denali.com.
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