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Xilinx and Wintegra Collaborate on LTE Baseband Targeted Design Platform for Faster, Lower Cost Development of 4G Wireless Basestations
New baseband and MAC architecture utilizing Xilinx FPGAs and
The platform combines the Xilinx(R) Virtex(R)-5 or Virtex-6 family of field programmable gate arrays (FPGAs) with
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Cost-Power Optimized Design
The key to the cost and power savings is the reduction in the number of devices in the basestation. The LTE baseband TDP combines multiple baseband and transport functions into fewer devices, including all the physical layer (PHY), media access control (MAC), and network and air interface security and encryption functions, as well as an optional Common Public Radio Interface serializer/deserializer (CPRI SERDES).
"Collaboration with
The software-defined nature of the platform enables basestation developers to 'future-proof' their products for the rapidly evolving world of cellular communications. The open framework facilitates integration of custom intellectual property components enabling developers to differentiate their products. The reprogrammable and reconfigurable architecture of the platform also makes it possible for operators to undertake field software upgrades without expensive hardware improvements or replacement programs.
Additionally, the processing headroom provided by the Xilinx FPGA-based physical layer opens the road to LTE-Advanced (LTE-A) technologies and integration of more complex, differentiating baseband algorithms, such as turbo equalization, baseband PAPR, and 4x4 MIMO decode. The
Integrated Test and Verification
Provisions are incorporated in the platform for monitoring standards compliance at multiple points throughout system development using the Agilent VSA software. The flexibility of the VSA software enables validation of the baseband development at both a pure software model level during the design concept phase and later using digitized signals from the
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Availability
The initial release of the LTE baseband TDP with prototypes using WinPath-2 silicon and Xilinx Virtex-5 FXT FPGAs is targeted for completion in
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