Silistix Announces Industry's First Mixed Synchronous/Asynchronous Network-on-Chip Solution in CHAIN(R)works 3.0
Silistix is no more in business
New Product Release Uniquely Combines Synchronous and Asynchronous Network Technologies to Solve Both Multi-Core Complexity and Deep Sub-Micron Device IssuesSAN JOSE, CA -- Mar 16, 2009 -- Silistix Inc. today announced CHAINworks 3.0, enabling architects and designers of complex chips to synthesize Networks-on-Chip (NoC) using both synchronous and asynchronous circuit techniques. This new release will be demonstrated at the MultiCore Expo Conference this week (March 16-19) at the Santa Clara Convention Center.
"Our customers are working at the dual bleeding edges of multi-function complexity and deep sub-micron device physics, to produce exciting new mobile computing and smartphone products," said David Fritz, CEO at Silistix. "Their previous on-chip interconnect solutions are failing to meet these new demands. We have developed our True GALS [Globally Asynchronous, Locally Synchronous] solution with the direct input of these key customers."
True GALS Network-on-Chip
NoC technology is rapidly replacing older interconnect technologies, such as shared buses or cross-bar switches, for complex multi-function devices. The fundamental reason is a network handles concurrent communication between many independent sub-systems more efficiently, with less contention for shared resources, than previous techniques. Today's complex devices are currently being implemented in semiconductor processes at 45nm and below, in order to reduce power and device size, while meeting increasing system performance requirements. However, at these deep sub-micron nodes, process variability and increasing wire delays make design implementation difficult, (especially closing timing between physical design and synthesis).
Silistix pioneered the use of asynchronous (clockless) networks to address this problem. In the CHAINworks 3.0 release, Silistix has added the capability to create local synchronous (clocked) networks. The combination of these technologies allows customers to adopt a True GALS approach to the on-chip interconnect, leveraging the low latency and area advantages of local synchronous subnets, with the low power, fewer wires and high tolerance to variability of a global asynchronous network. With CHAINworks 3.0, the customer can easily find the right combination of synchronous and asynchronous techniques to optimize the design while completely obviating global timing closure issues and delivering predictable power performance and area in the architecture phase.
Availability
Silistix' True GALS solution is available now in the CHAINworks 3.0 release.
About Silistix
Silistix, Inc. is a leading Silicon Intellectual Property (SIP) vendor, delivering predictable Network-on-Chip (NoC) solutions for managing chip complexity. Silistix CHAIN®works family of tools and IP libraries address timing closure, power management, and deep-sub-micron process variability while cutting chip design time and effort. Silistix is privately held and is backed by a number of venture firms and corporate investors, including Intel Capital. The company has offices in Manchester, England; San Jose, California; and Tokyo, Japan. For more information, visit www.silistix.com.
|
Related News
- Silistix Extends Its Industry Leading Asynchronous CHAIN(R)works Product Family With the Introduction of CHAINworks Sync
- Tenstorrent Expands Deployment of Arteris' Network-on-Chip IP to Next-Generation of Chiplet-Based AI Solutions
- TCL Joins Via Licensing Alliance's ATSC 3.0 Broadcasting Patent Pool
- Lightelligence Revolutionizes Big Data Interconnect with World's First Optical Network-on-Chip Processor
- Infineon's HYPERRAM™ 3.0 memory and Autotalks' 3rd generation chipset drive next-generation automotive V2X applications
Breaking News
- Silicon Creations Celebrates Milestone with Delivery of 1,000th Production License for Fractional-N PLL
- Kudelski IoT Launches Quantum-Resistant Security IP, Future-Proofing Semiconductors Against Emerging Quantum Threats
- Arteris and MIPS Partner on High-Performance RISC-V SoCs for Automotive, Datacenter and Edge AI
- NanoXplore acquires Dolphin Design's ASIC business and strengthens its strategic position in aerospace
- intoPIX and Media Links: Powering Next-Generation IP Media Transport with JPEG XS at InterBEE 2024
Most Popular
- Flex Logix Acquired By Analog Devices
- MIPS Releases P8700, Industry's First High-Performance AI-Enabled RISC-V Automotive CPU for ADAS and Autonomous Vehicles
- Tessolve to Acquire Germany's Dream Chip Technologies
- Oriole Networks Selects EnSilica as ASIC Partner and Contract Award for Photonics Controller ASIC
- Imagination DXS GPU officially certified as ASIL-B compliant
E-mail This Article | Printer-Friendly Page |