Genesys Testware supports multi-frequency at-speed testing to reduce defect levels in 0.25 micron ICs

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International Test Conference, 1999, Atlantic City, NJ, Booth 353

Genesys Testware supports multi-frequency at-speed testing to reduce defect levels in 0.25 micron ICs

Atlantic City, NJ, (September 28, 1999) -- Genesys Testware, Inc. today announced the addition of multi-frequency built-in at-speed testing capability to its Logic BistCore_TM product to reduce defect levels in 0.25 micron integrated circuits (IC). Logic BistCore_TM is a unique library of parameterized, synthesizable, register transfer level (RTL) designs to implement Built-In Self-Test (BIST) of hard cores and on-chip logic. "Semiconductor manufacturers are reporting much lower yields for ICs fabricated in a 0.25 micron process compared to those manufactured in a 0.35 micron process. Since the defect level increases exponentially with yield loss, it is essential to achieve nearly 100% defect coverage during manufacturing test. Delay defects which are a small fraction of the defect population have been mostly ignored so far. It is impossible for even the most expensive Automatic Test Equipment (ATE) to perform at-speed testing on ICs manufactured using 0.25 micron processes. Logic BistCore_TM can be used to detect delay faults in deep sub-micron ICs augmenting stuck-at fault tests created by an Automatic Test Pattern Generation (ATPG) tool.", said Bejoy G. Oomman, President of Genesys Testware. Logic BistCore_TM products work seamlessly with logic synthesis tools from Synopsys, Cadence, Avanti, and Mentor Graphics. Logic BistCore_TM products include parameterized self-checking testbenches which can be used to verify the operation of the BIST circuit using any VHDL (IEEE 1076-1993) or Verilog (IEEE 1364-1995) compliant simulator.
"Logic BIST complements scan ATPG in high level design flows to achieve high defect coverage", said Taher Abbasi, Vice President Products and Technology, Bytek Designs, Inc., a leading design services and training company. Bus frequency of many ICs fabricated in 0.25 micron processes exceed 100 Mhz, while their core frequency exceed 400 Mhz. System on Chip (SOC) designs also contain several reusable designs (cores) operating at different frequencies. For example an IC may have a 500 Mhz system clock, a 125 Mhz bus clock, and a 250 Mhz core clock. A BIST circuit with a very flexible clock control scheme is essential for performing at-speed tests on such complex ICs. Logic BistCore_TM can be used to create clocks whose period is an integer multiple of the master system clock using a sophisticated glitch-free clock gating network. Logic BistCore_TM can also be used to synchronize different scan chains on different clock domains operating at different frequencies. Designers of large ICs can continue to use their proven scan automatic test pattern generation (ATPG) processes to achieve high stuck-at fault coverage, while using Logic BistCore_TM to easily achieve high delay fault coverage. This approach also allows IC design managers to refine the integration of logic BIST tools into their design environment before rolling out logic BIST as their primary Design for Test (DFT) methodology.
Another major stumbling block to the widespread adoption of logic BIST in large ICs is the problem of signature corruption due to unkown states (X) produced by the circuit under test (CUT). Logic BistCore_TM incorporates elaborate response masking capabilities to solve this problem without making any changes to the CUT. Traditionally gate level test point insertion (TPI) has been used to improve the effectiveness of logic BIST. Modern logic synthesis tools now produce a gate level netlist and a placement file concurrently, with accurate area, timing and power estimations. Gate level TPI can invalidate synthesis results causing problems in timing convergence. Logic BistCore_TM also incorporates proprietary test circuitry which can achieve high fault coverage without gate level TPI.
Genesys Testware, Inc. was founded in October 1995 to improve the productivity of designers of large ICs, by providing comprehensive manufacturing test solutions which promote test reuse. Its unique TestCore_TMfamily of products has been successfully used in many customer designs. TestCore_TM consists of Memory BistCore_TM (BIST of embedded memories), Logic BistCore_TM (BIST of hard cores and on-chip logic) and Boundary ScanCore_TM (board test, core test integration and test pattern reuse). TestCore_TM is licensed as an IC Component Design to IC design groups as a perpetual site license with mandatory maintenance fee.
For more information on Genesys Testware or its products, please contact Bejoy G. Oomman, Genesys Testware, 76 Whitney Place, Fremont, CA 94539. Telephone : 510-661-0791, Fax: 510-498-8734, e-mail: bejoygo@genesystest.com, URL: http://www.genesystest.com.